Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef UFS_H |
| 8 | #define UFS_H |
Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
fengbaopeng | 44070ef | 2018-02-12 20:53:54 +0800 | [diff] [blame] | 11 | |
Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 12 | /* register map of UFSHCI */ |
| 13 | /* Controller Capabilities */ |
| 14 | #define CAP 0x00 |
| 15 | #define CAP_NUTRS_MASK 0x1F |
| 16 | |
| 17 | /* UFS Version */ |
| 18 | #define VER 0x08 |
| 19 | /* Host Controller Identification - Product ID */ |
| 20 | #define HCDDID 0x10 |
| 21 | /* Host Controller Identification Descriptor - Manufacturer ID */ |
| 22 | #define HCPMID 0x14 |
| 23 | /* Auto-Hibernate Idle Timer */ |
| 24 | #define AHIT 0x18 |
| 25 | /* Interrupt Status */ |
| 26 | #define IS 0x20 |
| 27 | /* Interrupt Enable */ |
| 28 | #define IE 0x24 |
| 29 | /* System Bus Fatal Error Status */ |
| 30 | #define UFS_INT_SBFES (1 << 17) |
| 31 | /* Host Controller Fatal Error Status */ |
| 32 | #define UFS_INT_HCFES (1 << 16) |
| 33 | /* UTP Error Status */ |
| 34 | #define UFS_INT_UTPES (1 << 12) |
| 35 | /* Device Fatal Error Status */ |
| 36 | #define UFS_INT_DFES (1 << 11) |
| 37 | /* UIC Command Completion Status */ |
| 38 | #define UFS_INT_UCCS (1 << 10) |
| 39 | /* UTP Task Management Request Completion Status */ |
| 40 | #define UFS_INT_UTMRCS (1 << 9) |
| 41 | /* UIC Link Startup Status */ |
| 42 | #define UFS_INT_ULSS (1 << 8) |
| 43 | /* UIC Link Lost Status */ |
| 44 | #define UFS_INT_ULLS (1 << 7) |
| 45 | /* UIC Hibernate Enter Status */ |
| 46 | #define UFS_INT_UHES (1 << 6) |
| 47 | /* UIC Hibernate Exit Status */ |
| 48 | #define UFS_INT_UHXS (1 << 5) |
| 49 | /* UIC Power Mode Status */ |
| 50 | #define UFS_INT_UPMS (1 << 4) |
| 51 | /* UIC Test Mode Status */ |
| 52 | #define UFS_INT_UTMS (1 << 3) |
| 53 | /* UIC Error */ |
| 54 | #define UFS_INT_UE (1 << 2) |
| 55 | /* UIC DME_ENDPOINTRESET Indication */ |
| 56 | #define UFS_INT_UDEPRI (1 << 1) |
| 57 | /* UTP Transfer Request Completion Status */ |
| 58 | #define UFS_INT_UTRCS (1 << 0) |
| 59 | |
| 60 | /* Host Controller Status */ |
| 61 | #define HCS 0x30 |
| 62 | #define HCS_UPMCRS_MASK (7 << 8) |
| 63 | #define HCS_PWR_LOCAL (1 << 8) |
| 64 | #define HCS_UCRDY (1 << 3) |
| 65 | #define HCS_UTMRLRDY (1 << 2) |
| 66 | #define HCS_UTRLRDY (1 << 1) |
| 67 | #define HCS_DP (1 << 0) |
| 68 | |
| 69 | /* Host Controller Enable */ |
| 70 | #define HCE 0x34 |
| 71 | #define HCE_ENABLE 1 |
| 72 | |
| 73 | /* Host UIC Error Code PHY Adapter Layer */ |
| 74 | #define UECPA 0x38 |
| 75 | /* Host UIC Error Code Data Link Layer */ |
| 76 | #define UECDL 0x3C |
| 77 | /* Host UIC Error Code Network Layer */ |
| 78 | #define UECN 0x40 |
| 79 | /* Host UIC Error Code Transport Layer */ |
| 80 | #define UECT 0x44 |
| 81 | /* Host UIC Error Code */ |
| 82 | #define UECDME 0x48 |
| 83 | /* UTP Transfer Request Interrupt Aggregation Control Register */ |
| 84 | #define UTRIACR 0x4C |
Justin Chadwell | 8294602 | 2019-07-03 14:15:22 +0100 | [diff] [blame] | 85 | #define UTRIACR_IAEN (1U << 31) |
Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 86 | #define UTRIACR_IAPWEN (1 << 24) |
| 87 | #define UTRIACR_IASB (1 << 20) |
| 88 | #define UTRIACR_CTR (1 << 16) |
| 89 | #define UTRIACR_IACTH(x) (((x) & 0x1F) << 8) |
| 90 | #define UTRIACR_IATOVAL(x) ((x) & 0xFF) |
| 91 | |
| 92 | /* UTP Transfer Request List Base Address */ |
| 93 | #define UTRLBA 0x50 |
| 94 | /* UTP Transfer Request List Base Address Upper 32-bits */ |
| 95 | #define UTRLBAU 0x54 |
| 96 | /* UTP Transfer Request List Door Bell Register */ |
| 97 | #define UTRLDBR 0x58 |
| 98 | /* UTP Transfer Request List Clear Register */ |
| 99 | #define UTRLCLR 0x5C |
| 100 | /* UTP Transfer Request List Run Stop Register */ |
| 101 | #define UTRLRSR 0x60 |
| 102 | #define UTMRLBA 0x70 |
| 103 | #define UTMRLBAU 0x74 |
| 104 | #define UTMRLDBR 0x78 |
| 105 | #define UTMRLCLR 0x7C |
| 106 | #define UTMRLRSR 0x80 |
| 107 | /* UIC Command */ |
| 108 | #define UICCMD 0x90 |
| 109 | /* UIC Command Argument 1 */ |
| 110 | #define UCMDARG1 0x94 |
| 111 | /* UIC Command Argument 2 */ |
| 112 | #define UCMDARG2 0x98 |
| 113 | /* UIC Command Argument 3 */ |
| 114 | #define UCMDARG3 0x9C |
| 115 | |
| 116 | #define UFS_BLOCK_SHIFT 12 /* 4KB */ |
| 117 | #define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT) |
| 118 | #define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1) |
| 119 | #define UFS_MAX_LUNS 8 |
| 120 | |
| 121 | /* UTP Transfer Request Descriptor */ |
| 122 | /* Command Type */ |
| 123 | #define CT_UFS_STORAGE 1 |
| 124 | #define CT_SCSI 0 |
| 125 | |
| 126 | /* Data Direction */ |
| 127 | #define DD_OUT 2 /* Device --> Host */ |
| 128 | #define DD_IN 1 /* Host --> Device */ |
| 129 | #define DD_NO_DATA_TRANSFER 0 |
| 130 | |
| 131 | #define UTP_TRD_SIZE 32 |
| 132 | |
| 133 | /* Transaction Type */ |
| 134 | #define TRANS_TYPE_HD (1 << 7) /* E2ECRC */ |
| 135 | #define TRANS_TYPE_DD (1 << 6) |
| 136 | #define TRANS_TYPE_CODE_MASK 0x3F |
| 137 | #define QUERY_RESPONSE_UPIU (0x36 << 0) |
| 138 | #define READY_TO_TRANSACTION_UPIU (0x31 << 0) |
| 139 | #define DATA_IN_UPIU (0x22 << 0) |
| 140 | #define RESPONSE_UPIU (0x21 << 0) |
| 141 | #define NOP_IN_UPIU (0x20 << 0) |
| 142 | #define QUERY_REQUEST_UPIU (0x16 << 0) |
| 143 | #define DATA_OUT_UPIU (0x02 << 0) |
| 144 | #define CMD_UPIU (0x01 << 0) |
| 145 | #define NOP_OUT_UPIU (0x00 << 0) |
| 146 | |
| 147 | #define OCS_SUCCESS 0x0 |
| 148 | #define OCS_INVALID_FUNC_ATTRIBUTE 0x1 |
| 149 | #define OCS_MISMATCH_REQUEST_SIZE 0x2 |
| 150 | #define OCS_MISMATCH_RESPONSE_SIZE 0x3 |
| 151 | #define OCS_PEER_COMMUNICATION_FAILURE 0x4 |
| 152 | #define OCS_ABORTED 0x5 |
| 153 | #define OCS_FATAL_ERROR 0x6 |
| 154 | #define OCS_MASK 0xF |
| 155 | |
| 156 | /* UIC Command */ |
| 157 | #define DME_GET 0x01 |
| 158 | #define DME_SET 0x02 |
| 159 | #define DME_PEER_GET 0x03 |
| 160 | #define DME_PEER_SET 0x04 |
| 161 | #define DME_POWERON 0x10 |
| 162 | #define DME_POWEROFF 0x11 |
| 163 | #define DME_ENABLE 0x12 |
| 164 | #define DME_RESET 0x14 |
| 165 | #define DME_ENDPOINTRESET 0x15 |
| 166 | #define DME_LINKSTARTUP 0x16 |
| 167 | #define DME_HIBERNATE_ENTER 0x17 |
| 168 | #define DME_HIBERNATE_EXIT 0x18 |
| 169 | #define DME_TEST_MODE 0x1A |
| 170 | |
| 171 | #define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF) |
| 172 | |
| 173 | #define CONFIG_RESULT_CODE_MASK 0xFF |
| 174 | |
| 175 | #define CDBCMD_TEST_UNIT_READY 0x00 |
| 176 | #define CDBCMD_READ_6 0x08 |
| 177 | #define CDBCMD_WRITE_6 0x0A |
| 178 | #define CDBCMD_START_STOP_UNIT 0x1B |
| 179 | #define CDBCMD_READ_CAPACITY_10 0x25 |
| 180 | #define CDBCMD_READ_10 0x28 |
| 181 | #define CDBCMD_WRITE_10 0x2A |
| 182 | #define CDBCMD_READ_16 0x88 |
| 183 | #define CDBCMD_WRITE_16 0x8A |
| 184 | #define CDBCMD_READ_CAPACITY_16 0x9E |
| 185 | #define CDBCMD_REPORT_LUNS 0xA0 |
| 186 | |
| 187 | #define UPIU_FLAGS_R (1 << 6) |
| 188 | #define UPIU_FLAGS_W (1 << 5) |
| 189 | #define UPIU_FLAGS_ATTR_MASK (3 << 0) |
| 190 | #define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */ |
| 191 | #define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */ |
| 192 | #define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */ |
| 193 | #define UPIU_FLAGS_ATTR_ACA (3 << 0) |
| 194 | #define UPIU_FLAGS_O (1 << 6) |
| 195 | #define UPIU_FLAGS_U (1 << 5) |
| 196 | #define UPIU_FLAGS_D (1 << 4) |
| 197 | |
| 198 | #define QUERY_FUNC_STD_READ 0x01 |
| 199 | #define QUERY_FUNC_STD_WRITE 0x81 |
| 200 | |
| 201 | #define QUERY_NOP 0x00 |
| 202 | #define QUERY_READ_DESC 0x01 |
| 203 | #define QUERY_WRITE_DESC 0x02 |
| 204 | #define QUERY_READ_ATTR 0x03 |
| 205 | #define QUERY_WRITE_ATTR 0x04 |
| 206 | #define QUERY_READ_FLAG 0x05 |
| 207 | #define QUERY_SET_FLAG 0x06 |
| 208 | #define QUERY_CLEAR_FLAG 0x07 |
| 209 | #define QUERY_TOGGLE_FLAG 0x08 |
| 210 | |
| 211 | #define RW_WITHOUT_CACHE 0x18 |
| 212 | |
| 213 | #define DESC_TYPE_DEVICE 0x00 |
| 214 | #define DESC_TYPE_CONFIGURATION 0x01 |
| 215 | #define DESC_TYPE_UNIT 0x02 |
| 216 | #define DESC_TYPE_INTERCONNECT 0x04 |
| 217 | #define DESC_TYPE_STRING 0x05 |
| 218 | |
fengbaopeng | 44070ef | 2018-02-12 20:53:54 +0800 | [diff] [blame] | 219 | #define DESC_DEVICE_MAX_SIZE 0x1F |
| 220 | #define DEVICE_DESC_PARAM_MANF_ID 0x18 |
| 221 | |
Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 222 | #define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */ |
| 223 | #define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */ |
| 224 | |
| 225 | #define DEVICE_DESCRIPTOR_LEN 0x40 |
| 226 | #define UNIT_DESCRIPTOR_LEN 0x23 |
| 227 | |
| 228 | #define QUERY_RESP_SUCCESS 0x00 |
| 229 | #define QUERY_RESP_OPCODE 0xFE |
| 230 | #define QUERY_RESP_GENERAL_FAIL 0xFF |
| 231 | |
| 232 | #define SENSE_KEY_NO_SENSE 0x00 |
| 233 | #define SENSE_KEY_RECOVERED_ERROR 0x01 |
| 234 | #define SENSE_KEY_NOT_READY 0x02 |
| 235 | #define SENSE_KEY_MEDIUM_ERROR 0x03 |
| 236 | #define SENSE_KEY_HARDWARE_ERROR 0x04 |
| 237 | #define SENSE_KEY_ILLEGAL_REQUEST 0x05 |
| 238 | #define SENSE_KEY_UNIT_ATTENTION 0x06 |
| 239 | #define SENSE_KEY_DATA_PROTECT 0x07 |
| 240 | #define SENSE_KEY_BLANK_CHECK 0x08 |
| 241 | #define SENSE_KEY_VENDOR_SPECIFIC 0x09 |
| 242 | #define SENSE_KEY_COPY_ABORTED 0x0A |
| 243 | #define SENSE_KEY_ABORTED_COMMAND 0x0B |
| 244 | #define SENSE_KEY_VOLUME_OVERFLOW 0x0D |
| 245 | #define SENSE_KEY_MISCOMPARE 0x0E |
| 246 | |
| 247 | #define SENSE_DATA_VALID 0x70 |
| 248 | #define SENSE_DATA_LENGTH 18 |
| 249 | |
| 250 | #define READ_CAPACITY_LENGTH 8 |
| 251 | |
| 252 | #define FLAG_DEVICE_INIT 0x01 |
| 253 | |
fengbaopeng | 44070ef | 2018-02-12 20:53:54 +0800 | [diff] [blame] | 254 | #define UFS_VENDOR_SKHYNIX U(0x1AD) |
| 255 | |
| 256 | #define MAX_MODEL_LEN 16 |
| 257 | /** |
| 258 | * ufs_dev_desc - ufs device details from the device descriptor |
| 259 | * @wmanufacturerid: card details |
| 260 | * @model: card model |
| 261 | */ |
| 262 | struct ufs_dev_desc { |
| 263 | uint16_t wmanufacturerid; |
| 264 | int8_t model[MAX_MODEL_LEN + 1]; |
| 265 | }; |
| 266 | |
Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 267 | /* UFS Driver Flags */ |
| 268 | #define UFS_FLAGS_SKIPINIT (1 << 0) |
fengbaopeng | 44070ef | 2018-02-12 20:53:54 +0800 | [diff] [blame] | 269 | #define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2) |
Haojian Zhuang | 20cd323 | 2017-05-31 11:00:15 +0800 | [diff] [blame] | 270 | |
| 271 | typedef struct sense_data { |
| 272 | uint8_t resp_code : 7; |
| 273 | uint8_t valid : 1; |
| 274 | uint8_t reserved0; |
| 275 | uint8_t sense_key : 4; |
| 276 | uint8_t reserved1 : 1; |
| 277 | uint8_t ili : 1; |
| 278 | uint8_t eom : 1; |
| 279 | uint8_t file_mark : 1; |
| 280 | uint8_t info[4]; |
| 281 | uint8_t asl; |
| 282 | uint8_t cmd_spec_len[4]; |
| 283 | uint8_t asc; |
| 284 | uint8_t ascq; |
| 285 | uint8_t fruc; |
| 286 | uint8_t sense_key_spec0 : 7; |
| 287 | uint8_t sksv : 1; |
| 288 | uint8_t sense_key_spec1; |
| 289 | uint8_t sense_key_spec2; |
| 290 | } sense_data_t; |
| 291 | |
| 292 | /* UTP Transfer Request Descriptor */ |
| 293 | typedef struct utrd_header { |
| 294 | uint32_t reserved0 : 24; |
| 295 | uint32_t i : 1; /* interrupt */ |
| 296 | uint32_t dd : 2; /* data direction */ |
| 297 | uint32_t reserved1 : 1; |
| 298 | uint32_t ct : 4; /* command type */ |
| 299 | uint32_t reserved2; |
| 300 | uint32_t ocs : 8; /* Overall Command Status */ |
| 301 | uint32_t reserved3 : 24; |
| 302 | uint32_t reserved4; |
| 303 | uint32_t ucdba; /* aligned to 128-byte */ |
| 304 | uint32_t ucdbau; /* Upper 32-bits */ |
| 305 | uint32_t rul : 16; /* Response UPIU Length */ |
| 306 | uint32_t ruo : 16; /* Response UPIU Offset */ |
| 307 | uint32_t prdtl : 16; /* PRDT Length */ |
| 308 | uint32_t prdto : 16; /* PRDT Offset */ |
| 309 | } utrd_header_t; /* 8 words with little endian */ |
| 310 | |
| 311 | /* UTP Task Management Request Descriptor */ |
| 312 | typedef struct utp_utmrd { |
| 313 | /* 4 words with little endian */ |
| 314 | uint32_t reserved0 : 24; |
| 315 | uint32_t i : 1; /* interrupt */ |
| 316 | uint32_t reserved1 : 7; |
| 317 | uint32_t reserved2; |
| 318 | uint32_t ocs : 8; /* Overall Command Status */ |
| 319 | uint32_t reserved3 : 24; |
| 320 | uint32_t reserved4; |
| 321 | |
| 322 | /* followed by 8 words UPIU with big endian */ |
| 323 | |
| 324 | /* followed by 8 words Response UPIU with big endian */ |
| 325 | } utp_utmrd_t; |
| 326 | |
| 327 | /* NOP OUT UPIU */ |
| 328 | typedef struct nop_out_upiu { |
| 329 | uint8_t trans_type; |
| 330 | uint8_t flags; |
| 331 | uint8_t reserved0; |
| 332 | uint8_t task_tag; |
| 333 | uint8_t reserved1; |
| 334 | uint8_t reserved2; |
| 335 | uint8_t reserved3; |
| 336 | uint8_t reserved4; |
| 337 | uint8_t total_ehs_len; |
| 338 | uint8_t reserved5; |
| 339 | uint16_t data_segment_len; |
| 340 | uint32_t reserved6; |
| 341 | uint32_t reserved7; |
| 342 | uint32_t reserved8; |
| 343 | uint32_t reserved9; |
| 344 | uint32_t reserved10; |
| 345 | uint32_t e2ecrc; |
| 346 | } nop_out_upiu_t; /* 36 bytes with big endian */ |
| 347 | |
| 348 | /* NOP IN UPIU */ |
| 349 | typedef struct nop_in_upiu { |
| 350 | uint8_t trans_type; |
| 351 | uint8_t flags; |
| 352 | uint8_t reserved0; |
| 353 | uint8_t task_tag; |
| 354 | uint8_t reserved1; |
| 355 | uint8_t reserved2; |
| 356 | uint8_t response; |
| 357 | uint8_t reserved3; |
| 358 | uint8_t total_ehs_len; |
| 359 | uint8_t dev_info; |
| 360 | uint16_t data_segment_len; |
| 361 | uint32_t reserved4; |
| 362 | uint32_t reserved5; |
| 363 | uint32_t reserved6; |
| 364 | uint32_t reserved7; |
| 365 | uint32_t reserved8; |
| 366 | uint32_t e2ecrc; |
| 367 | } nop_in_upiu_t; /* 36 bytes with big endian */ |
| 368 | |
| 369 | /* Command UPIU */ |
| 370 | typedef struct cmd_upiu { |
| 371 | uint8_t trans_type; |
| 372 | uint8_t flags; |
| 373 | uint8_t lun; |
| 374 | uint8_t task_tag; |
| 375 | uint8_t cmd_set_type; |
| 376 | uint8_t reserved0; |
| 377 | uint8_t reserved1; |
| 378 | uint8_t reserved2; |
| 379 | uint8_t total_ehs_len; |
| 380 | uint8_t reserved3; |
| 381 | uint16_t data_segment_len; |
| 382 | uint32_t exp_data_trans_len; |
| 383 | /* |
| 384 | * A CDB has a fixed length of 16bytes or a variable length |
| 385 | * of between 12 and 260 bytes |
| 386 | */ |
| 387 | uint8_t cdb[16]; /* little endian */ |
| 388 | } cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */ |
| 389 | |
| 390 | typedef struct query_desc { |
| 391 | uint8_t opcode; |
| 392 | uint8_t idn; |
| 393 | uint8_t index; |
| 394 | uint8_t selector; |
| 395 | uint8_t reserved0[2]; |
| 396 | uint16_t length; |
| 397 | uint32_t reserved2[2]; |
| 398 | } query_desc_t; /* 16 bytes with big endian */ |
| 399 | |
| 400 | typedef struct query_flag { |
| 401 | uint8_t opcode; |
| 402 | uint8_t idn; |
| 403 | uint8_t index; |
| 404 | uint8_t selector; |
| 405 | uint8_t reserved0[7]; |
| 406 | uint8_t value; |
| 407 | uint32_t reserved8; |
| 408 | } query_flag_t; /* 16 bytes with big endian */ |
| 409 | |
| 410 | typedef struct query_attr { |
| 411 | uint8_t opcode; |
| 412 | uint8_t idn; |
| 413 | uint8_t index; |
| 414 | uint8_t selector; |
| 415 | uint8_t reserved0[4]; |
| 416 | uint32_t value; /* little endian */ |
| 417 | uint32_t reserved4; |
| 418 | } query_attr_t; /* 16 bytes with big endian except for value */ |
| 419 | |
| 420 | /* Query Request UPIU */ |
| 421 | typedef struct query_upiu { |
| 422 | uint8_t trans_type; |
| 423 | uint8_t flags; |
| 424 | uint8_t reserved0; |
| 425 | uint8_t task_tag; |
| 426 | uint8_t reserved1; |
| 427 | uint8_t query_func; |
| 428 | uint8_t reserved2; |
| 429 | uint8_t reserved3; |
| 430 | uint8_t total_ehs_len; |
| 431 | uint8_t reserved4; |
| 432 | uint16_t data_segment_len; |
| 433 | /* Transaction Specific Fields */ |
| 434 | union { |
| 435 | query_desc_t desc; |
| 436 | query_flag_t flag; |
| 437 | query_attr_t attr; |
| 438 | } ts; |
| 439 | uint32_t reserved5; |
| 440 | } query_upiu_t; /* 32 bytes with big endian */ |
| 441 | |
| 442 | /* Query Response UPIU */ |
| 443 | typedef struct query_resp_upiu { |
| 444 | uint8_t trans_type; |
| 445 | uint8_t flags; |
| 446 | uint8_t reserved0; |
| 447 | uint8_t task_tag; |
| 448 | uint8_t reserved1; |
| 449 | uint8_t query_func; |
| 450 | uint8_t query_resp; |
| 451 | uint8_t reserved2; |
| 452 | uint8_t total_ehs_len; |
| 453 | uint8_t dev_info; |
| 454 | uint16_t data_segment_len; |
| 455 | union { |
| 456 | query_desc_t desc; |
| 457 | query_flag_t flag; |
| 458 | query_attr_t attr; |
| 459 | } ts; |
| 460 | uint32_t reserved3; |
| 461 | } query_resp_upiu_t; /* 32 bytes with big endian */ |
| 462 | |
| 463 | /* Response UPIU */ |
| 464 | typedef struct resp_upiu { |
| 465 | uint8_t trans_type; |
| 466 | uint8_t flags; |
| 467 | uint8_t lun; |
| 468 | uint8_t task_tag; |
| 469 | uint8_t cmd_set_type; |
| 470 | uint8_t reserved0; |
| 471 | uint8_t reserved1; |
| 472 | uint8_t status; |
| 473 | uint8_t total_ehs_len; |
| 474 | uint8_t dev_info; |
| 475 | uint16_t data_segment_len; |
| 476 | uint32_t res_trans_cnt; /* Residual Transfer Count */ |
| 477 | uint32_t reserved2[4]; |
| 478 | uint16_t sense_data_len; |
| 479 | union { |
| 480 | uint8_t sense_data[18]; |
| 481 | sense_data_t sense; |
| 482 | } sd; |
| 483 | } resp_upiu_t; /* 52 bytes with big endian */ |
| 484 | |
| 485 | typedef struct cmd_info { |
| 486 | uintptr_t buf; |
| 487 | size_t length; |
| 488 | int lba; |
| 489 | uint8_t op; |
| 490 | uint8_t direction; |
| 491 | uint8_t lun; |
| 492 | } cmd_info_t; |
| 493 | |
| 494 | typedef struct utp_utrd { |
| 495 | uintptr_t header; /* utrd_header_t */ |
| 496 | uintptr_t upiu; |
| 497 | uintptr_t resp_upiu; |
| 498 | uintptr_t prdt; |
| 499 | size_t size_upiu; |
| 500 | size_t size_resp_upiu; |
| 501 | size_t size_prdt; |
| 502 | int task_tag; |
| 503 | } utp_utrd_t; |
| 504 | |
| 505 | /* Physical Region Description Table */ |
| 506 | typedef struct prdt { |
| 507 | uint32_t dba; /* Data Base Address */ |
| 508 | uint32_t dbau; /* Data Base Address Upper 32-bits */ |
| 509 | uint32_t reserved0; |
| 510 | uint32_t dbc : 18; /* Data Byte Count */ |
| 511 | uint32_t reserved1 : 14; |
| 512 | } prdt_t; |
| 513 | |
| 514 | typedef struct uic_cmd { |
| 515 | uint32_t op; |
| 516 | uint32_t arg1; |
| 517 | uint32_t arg2; |
| 518 | uint32_t arg3; |
| 519 | } uic_cmd_t; |
| 520 | |
| 521 | typedef struct ufs_params { |
| 522 | uintptr_t reg_base; |
| 523 | uintptr_t desc_base; |
| 524 | size_t desc_size; |
| 525 | unsigned long flags; |
| 526 | } ufs_params_t; |
| 527 | |
| 528 | typedef struct ufs_ops { |
| 529 | int (*phy_init)(ufs_params_t *params); |
| 530 | int (*phy_set_pwr_mode)(ufs_params_t *params); |
| 531 | } ufs_ops_t; |
| 532 | |
| 533 | int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd); |
| 534 | int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val); |
| 535 | int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val); |
| 536 | |
| 537 | unsigned int ufs_read_attr(int idn); |
| 538 | void ufs_write_attr(int idn, unsigned int value); |
| 539 | unsigned int ufs_read_flag(int idn); |
| 540 | void ufs_set_flag(int idn); |
| 541 | void ufs_clear_flag(int idn); |
| 542 | void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size); |
| 543 | void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size); |
| 544 | size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size); |
| 545 | size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size); |
| 546 | int ufs_init(const ufs_ops_t *ops, ufs_params_t *params); |
| 547 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 548 | #endif /* UFS_H */ |