| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 1 | /* |
| Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Arm Limited. All rights reserved. |
| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_A78C_H |
| 8 | #define CORTEX_A78C_H |
| 9 | |
| 10 | |
| 11 | #define CORTEX_A78C_MIDR U(0x410FD4B1) |
| 12 | |
| Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 13 | /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ |
| 14 | #define CORTEX_A78C_BHB_LOOP_COUNT U(32) |
| 15 | |
| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 16 | /******************************************************************************* |
| Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 17 | * CPU Auxiliary Control register 2 specific definitions. |
| 18 | * ****************************************************************************/ |
| 19 | #define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| Akram Ahmad | fbc1edb | 2022-09-06 11:23:25 +0100 | [diff] [blame] | 20 | #define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) |
| Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 21 | #define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) |
| 22 | |
| 23 | /******************************************************************************* |
| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 24 | * CPU Extended Control register specific definitions. |
| 25 | ******************************************************************************/ |
| 26 | #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 |
| Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 27 | #define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) |
| 28 | #define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) |
| Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 29 | #define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) |
| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 30 | |
| 31 | /******************************************************************************* |
| 32 | * CPU Power Control register specific definitions |
| 33 | ******************************************************************************/ |
| 34 | #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 35 | #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) |
| 36 | |
| Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 37 | /******************************************************************************* |
| Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 38 | * CPU Auxiliary Control register 3 specific definitions. |
| 39 | ******************************************************************************/ |
| 40 | #define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 |
| 41 | |
| 42 | /******************************************************************************* |
| Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 43 | * CPU Implementation Specific Selected Instruction registers |
| 44 | ******************************************************************************/ |
| 45 | #define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 46 | #define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 |
| 47 | #define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 |
| 48 | #define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 |
| 49 | |
| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 50 | #endif /* CORTEX_A78C_H */ |