| Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 1 | /* |
| Yann Gautier | bc9f0fd | 2022-06-30 11:33:27 +0200 | [diff] [blame] | 2 | * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved |
| Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP1_STM32IMAGE_DEF_H |
| 8 | #define STM32MP1_STM32IMAGE_DEF_H |
| 9 | |
| Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 10 | #ifdef AARCH32_SP_OPTEE |
| Yann Gautier | bc9f0fd | 2022-06-30 11:33:27 +0200 | [diff] [blame] | 11 | #if STM32MP15_OPTEE_RSV_SHM |
| Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 12 | #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ |
| 13 | #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ |
| 14 | #else |
| Yann Gautier | bc9f0fd | 2022-06-30 11:33:27 +0200 | [diff] [blame] | 15 | #define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ |
| 16 | #define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */ |
| 17 | #endif |
| 18 | #else |
| Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 19 | #define STM32MP_DDR_S_SIZE U(0) |
| 20 | #define STM32MP_DDR_SHMEM_SIZE U(0) |
| 21 | #endif |
| 22 | |
| Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 23 | #define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */ |
| 24 | #define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ |
| 25 | |
| 26 | #ifdef AARCH32_SP_OPTEE |
| 27 | #define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE |
| 28 | |
| 29 | #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ |
| 30 | STM32MP_SEC_SYSRAM_SIZE - \ |
| 31 | STM32MP_BL2_SIZE) |
| 32 | |
| 33 | /* OP-TEE loads from SYSRAM base to BL2 DTB start address */ |
| 34 | #define STM32MP_OPTEE_BASE STM32MP_BL32_BASE |
| 35 | #define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ |
| 36 | STM32MP_BL2_SIZE - STM32MP_DTB_SIZE) |
| 37 | #define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE |
| 38 | #else /* AARCH32_SP_OPTEE */ |
| 39 | #define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */ |
| 40 | |
| 41 | #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ |
| 42 | STM32MP_SEC_SYSRAM_SIZE - \ |
| 43 | STM32MP_BL32_SIZE) |
| 44 | |
| 45 | #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ |
| 46 | STM32MP_BL2_SIZE) |
| 47 | #endif /* AARCH32_SP_OPTEE */ |
| 48 | |
| 49 | /* DTB initialization value */ |
| 50 | #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ |
| 51 | STM32MP_DTB_SIZE) |
| 52 | |
| 53 | /* |
| 54 | * MAX_MMAP_REGIONS is usually: |
| 55 | * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup |
| 56 | */ |
| 57 | #if defined(IMAGE_BL32) |
| 58 | #define MAX_MMAP_REGIONS 6 |
| 59 | #endif |
| 60 | |
| 61 | /******************************************************************************* |
| 62 | * STM32MP1 RAW partition offset for MTD devices |
| 63 | ******************************************************************************/ |
| 64 | #define STM32MP_NOR_BL33_OFFSET U(0x00080000) |
| 65 | #ifdef AARCH32_SP_OPTEE |
| 66 | #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) |
| 67 | #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) |
| 68 | #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) |
| 69 | #endif |
| 70 | |
| 71 | #define STM32MP_NAND_BL33_OFFSET U(0x00200000) |
| 72 | #ifdef AARCH32_SP_OPTEE |
| 73 | #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) |
| 74 | #define STM32MP_NAND_TEED_OFFSET U(0x00680000) |
| 75 | #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) |
| 76 | #endif |
| 77 | |
| 78 | #endif /* STM32MP1_STM32IMAGE_DEF_H */ |