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Andre Przywara6d471e12019-07-09 11:25:57 +01001/*
Mario Bălănicăcb759ff2023-12-06 21:36:25 +02002 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
Andre Przywara6d471e12019-07-09 11:25:57 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef RPI_HW_H
8#define RPI_HW_H
9
10#include <lib/utils_def.h>
11
12/*
13 * Peripherals
14 */
15
Jeremy Linton58c99742020-11-18 10:17:15 -060016#define RPI_IO_BASE ULL(0xFC000000)
17#define RPI_IO_SIZE ULL(0x04000000)
18
19#define RPI_LEGACY_BASE (ULL(0x02000000) + RPI_IO_BASE)
Andre Przywara6d471e12019-07-09 11:25:57 +010020
21/*
22 * ARM <-> VideoCore mailboxes
23 */
24#define RPI3_MBOX_OFFSET ULL(0x0000B880)
Jeremy Linton58c99742020-11-18 10:17:15 -060025#define RPI3_MBOX_BASE (RPI_LEGACY_BASE + RPI3_MBOX_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010026
27/*
28 * Power management, reset controller, watchdog.
29 */
30#define RPI3_IO_PM_OFFSET ULL(0x00100000)
Jeremy Linton58c99742020-11-18 10:17:15 -060031#define RPI3_PM_BASE (RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010032
33/*
Andre Przywara6d471e12019-07-09 11:25:57 +010034 * Hardware random number generator.
35 */
36#define RPI3_IO_RNG_OFFSET ULL(0x00104000)
Jeremy Linton58c99742020-11-18 10:17:15 -060037#define RPI3_RNG_BASE (RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010038
39/*
Andre Przywara9ba6bb02020-03-10 12:34:56 +000040 * Serial ports:
41 * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
42 * There is also a PL011 UART, multiplexed to the same pins.
Andre Przywara6d471e12019-07-09 11:25:57 +010043 */
Andre Przywara57ccecc2020-03-10 12:33:16 +000044#define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040)
Jeremy Linton58c99742020-11-18 10:17:15 -060045#define RPI4_MINI_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET)
Andre Przywara9ba6bb02020-03-10 12:34:56 +000046#define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000)
Jeremy Linton58c99742020-11-18 10:17:15 -060047#define RPI4_PL011_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET)
Andre Przywara9ba6bb02020-03-10 12:34:56 +000048#define RPI4_PL011_UART_CLOCK ULL(48000000)
Andre Przywara6d471e12019-07-09 11:25:57 +010049
50/*
51 * GPIO controller
52 */
53#define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
Jeremy Linton58c99742020-11-18 10:17:15 -060054#define RPI3_GPIO_BASE (RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010055
56/*
57 * SDHost controller
58 */
59#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000)
Jeremy Linton58c99742020-11-18 10:17:15 -060060#define RPI3_SDHOST_BASE (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010061
62/*
63 * GIC interrupt controller
64 */
65#define RPI_HAVE_GIC
66#define RPI4_GIC_GICD_BASE ULL(0xff841000)
67#define RPI4_GIC_GICC_BASE ULL(0xff842000)
68
69#define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000)
70#define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008)
71
72#endif /* RPI_HW_H */