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developer2189d3a2020-04-17 17:14:23 +08001#
2# Copyright (c) 2020, MediaTek Inc. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7MTK_PLAT := plat/mediatek
8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
9
10PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
developer404e08b2020-09-18 09:32:31 +080011 -I${MTK_PLAT_SOC}/include/ \
12 -I${MTK_PLAT_SOC}/drivers/ \
developera6304632020-09-08 14:36:07 +080013 -I${MTK_PLAT_SOC}/drivers/dcm \
developerbd481152020-11-02 10:45:34 +080014 -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
developer86ada3c2020-07-03 09:19:06 +080015 -I${MTK_PLAT_SOC}/drivers/gpio/ \
developera444a202020-06-15 16:41:03 +080016 -I${MTK_PLAT_SOC}/drivers/mcdi/ \
developer74cf3ec2020-08-12 16:31:06 +080017 -I${MTK_PLAT_SOC}/drivers/pmic/ \
developer4d055072020-08-25 22:31:14 +080018 -I${MTK_PLAT_SOC}/drivers/ptp3/ \
developerbeab2d72020-10-14 20:14:37 +080019 -I${MTK_PLAT_SOC}/drivers/rtc/ \
developer31f56a72020-06-16 13:28:28 +080020 -I${MTK_PLAT_SOC}/drivers/spmc/ \
developer0df1c3c2020-08-01 16:23:12 +080021 -I${MTK_PLAT_SOC}/drivers/timer/ \
22 -I${MTK_PLAT_SOC}/drivers/uart/
developer2189d3a2020-04-17 17:14:23 +080023
developerf9b56842020-06-09 13:38:35 +080024GICV3_SUPPORT_GIC600 := 1
developer2189d3a2020-04-17 17:14:23 +080025include drivers/arm/gic/v3/gicv3.mk
26include lib/xlat_tables_v2/xlat_tables.mk
27
28PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \
29 ${XLAT_TABLES_LIB_SRCS} \
30 plat/common/aarch64/crash_console_helpers.S \
31 plat/common/plat_psci_common.c
32
33BL31_SOURCES += common/desc_image_load.c \
developerf13d6492020-08-05 13:53:59 +080034 drivers/delay_timer/delay_timer.c \
35 drivers/delay_timer/generic_delay_timer.c \
developer2189d3a2020-04-17 17:14:23 +080036 drivers/ti/uart/aarch64/16550_console.S \
developer404e08b2020-09-18 09:32:31 +080037 drivers/gpio/gpio.c \
developer2189d3a2020-04-17 17:14:23 +080038 lib/bl_aux_params/bl_aux_params.c \
39 lib/cpus/aarch64/cortex_a55.S \
40 lib/cpus/aarch64/cortex_a76.S \
41 plat/common/plat_gicv3.c \
developer74cf3ec2020-08-12 16:31:06 +080042 ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
developerbeab2d72020-10-14 20:14:37 +080043 ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
developer0df1c3c2020-08-01 16:23:12 +080044 ${MTK_PLAT}/common/drivers/uart/uart.c \
developer2189d3a2020-04-17 17:14:23 +080045 ${MTK_PLAT}/common/mtk_plat_common.c \
developera84a44a2020-08-19 17:20:15 +080046 ${MTK_PLAT}/common/mtk_sip_svc.c \
developer2189d3a2020-04-17 17:14:23 +080047 ${MTK_PLAT}/common/params_setup.c \
48 ${MTK_PLAT_SOC}/aarch64/platform_common.c \
49 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
50 ${MTK_PLAT_SOC}/bl31_plat_setup.c \
developer74cf3ec2020-08-12 16:31:06 +080051 ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
developerbeab2d72020-10-14 20:14:37 +080052 ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
developer2189d3a2020-04-17 17:14:23 +080053 ${MTK_PLAT_SOC}/plat_pm.c \
developerf9b56842020-06-09 13:38:35 +080054 ${MTK_PLAT_SOC}/plat_topology.c \
developer404e08b2020-09-18 09:32:31 +080055 ${MTK_PLAT_SOC}/plat_mt_gic.c \
developer28d70382019-12-19 15:58:20 +080056 ${MTK_PLAT_SOC}/plat_mt_cirq.c \
developera84a44a2020-08-19 17:20:15 +080057 ${MTK_PLAT_SOC}/plat_sip_calls.c \
developera6304632020-09-08 14:36:07 +080058 ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
59 ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
developerbd481152020-11-02 10:45:34 +080060 ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
developer86ada3c2020-07-03 09:19:06 +080061 ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
developera444a202020-06-15 16:41:03 +080062 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
63 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
64 ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
developer4d055072020-08-25 22:31:14 +080065 ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
developer31f56a72020-06-16 13:28:28 +080066 ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
developer86ada3c2020-07-03 09:19:06 +080067 ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
developer2189d3a2020-04-17 17:14:23 +080068
developer2189d3a2020-04-17 17:14:23 +080069# Configs for A76 and A55
70HW_ASSISTED_COHERENCY := 1
71USE_COHERENT_MEM := 0
72CTX_INCLUDE_AARCH32_REGS := 0
73
74# indicate the reset vector address can be programmed
75PROGRAMMABLE_RESET_ADDRESS := 1
76
77COLD_BOOT_SINGLE_CPU := 1
78
79MACH_MT8192 := 1
80$(eval $(call add_define,MACH_MT8192))
81
82include lib/coreboot/coreboot.mk
83