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Sumit Garg82d45c12018-06-15 13:41:59 +05301/*
Aditya Angadi7b424ba2019-12-31 10:14:32 +05302 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Sumit Garg82d45c12018-06-15 13:41:59 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Sumit Garg82d45c12018-06-15 13:41:59 +05309
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
11#include <plat/common/common_def.h>
Sumit Garg82d45c12018-06-15 13:41:59 +053012
Sumit Garg4d4df112018-06-15 14:43:35 +053013/* CPU topology */
Deepika Bhavnani353ac952019-12-13 10:51:28 -060014#define PLAT_MAX_CORES_PER_CLUSTER U(2)
15#define PLAT_CLUSTER_COUNT U(12)
Sumit Garg4d4df112018-06-15 14:43:35 +053016#define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \
17 PLAT_MAX_CORES_PER_CLUSTER)
18
Masahisa Kojimaebfd8eb2019-03-07 10:41:54 +090019/* Macros to read the SQ power domain state */
20#define SQ_PWR_LVL0 MPIDR_AFFLVL0
21#define SQ_PWR_LVL1 MPIDR_AFFLVL1
22#define SQ_PWR_LVL2 MPIDR_AFFLVL2
23
24#define SQ_CORE_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL0]
25#define SQ_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL1]
26#define SQ_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\
27 (state)->pwr_domain_state[SQ_PWR_LVL2] : 0)
28
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010029#define PLAT_MAX_PWR_LVL U(1)
30#define PLAT_MAX_RET_STATE U(1)
31#define PLAT_MAX_OFF_STATE U(2)
Sumit Garg754073f2018-06-15 15:29:02 +053032
33#define SQ_LOCAL_STATE_RUN 0
34#define SQ_LOCAL_STATE_RET 1
35#define SQ_LOCAL_STATE_OFF 2
36
Sumit Garg82d45c12018-06-15 13:41:59 +053037#define CACHE_WRITEBACK_SHIFT 6
38#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
39
Sumit Garg470255b2018-06-15 15:10:16 +053040#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
41#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
Ard Biesheuvelc0415c62018-12-29 19:44:35 +010042#define MAX_XLAT_TABLES 8
43#define MAX_MMAP_REGIONS 8
Sumit Garg470255b2018-06-15 15:10:16 +053044
Sumit Garg82d45c12018-06-15 13:41:59 +053045#define PLATFORM_STACK_SIZE 0x400
46
47#define BL31_BASE 0x04000000
48#define BL31_SIZE 0x00080000
49#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
50
Ard Biesheuvel18498352018-12-29 19:40:31 +010051#define BL32_BASE 0xfc000000
Ard Biesheuvelc0415c62018-12-29 19:44:35 +010052#define BL32_SIZE 0x03c00000
53#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
Ard Biesheuvel18498352018-12-29 19:40:31 +010054
Sumit Gargbda9d3c2018-06-15 14:50:19 +053055#define PLAT_SQ_CCN_BASE 0x32000000
56#define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \
57 0, /* Cluster 0 */ \
58 18, /* Cluster 1 */ \
59 11, /* Cluster 2 */ \
60 29, /* Cluster 3 */ \
61 35, /* Cluster 4 */ \
62 17, /* Cluster 5 */ \
63 12, /* Cluster 6 */ \
64 30, /* Cluster 7 */ \
65 14, /* Cluster 8 */ \
66 32, /* Cluster 9 */ \
67 15, /* Cluster 10 */ \
68 33 /* Cluster 11 */
69
Sumit Garg84711f92018-06-15 14:34:42 +053070/* UART related constants */
71#define PLAT_SQ_BOOT_UART_BASE 0x2A400000
72#define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000
73#define SQ_CONSOLE_BAUDRATE 115200
74
Sumit Garg58ed23d2018-06-15 15:02:31 +053075#define SQ_SYS_CNTCTL_BASE 0x2a430000
76
77#define SQ_SYS_TIMCTL_BASE 0x2a810000
78#define PLAT_SQ_NSTIMER_FRAME_ID 0
79
Ard Biesheuvel6fc122f2018-06-15 15:25:42 +053080#define DRAMINFO_BASE 0x2E00FFC0
81
Sumit Gargfe717612018-06-15 15:17:10 +053082#define PLAT_SQ_MHU_BASE 0x45000000
83
Sumit Garg0f18bc42018-06-15 15:20:53 +053084#define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000
85#define SCPI_CMD_GET_DRAMINFO 0x1
86
Sumit Garg38172022018-06-15 13:48:11 +053087#define SQ_BOOT_CFG_ADDR 0x45410000
88#define PLAT_SQ_PRIMARY_CPU_SHIFT 8
89#define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6
90
Sumit Gargc412c2c2018-06-15 14:58:25 +053091#define PLAT_SQ_GICD_BASE 0x30000000
92#define PLAT_SQ_GICR_BASE 0x30400000
93
Sumit Garg754073f2018-06-15 15:29:02 +053094#define PLAT_SQ_GPIO_BASE 0x51000000
95
Ard Biesheuvelc0415c62018-12-29 19:44:35 +010096#define PLAT_SPM_BUF_BASE (BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE)
97#define PLAT_SPM_BUF_SIZE ULL(0x10000)
98#define PLAT_SPM_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \
99 PLAT_SPM_BUF_BASE, \
100 PLAT_SPM_BUF_SIZE, \
101 MT_RO_DATA | MT_SECURE | \
102 MT_USER, PAGE_SIZE)
103
104#define PLAT_SP_IMAGE_NS_BUF_BASE BL32_LIMIT
105#define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000)
106#define PLAT_SP_IMAGE_NS_BUF_MMAP MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \
107 PLAT_SP_IMAGE_NS_BUF_BASE, \
108 PLAT_SP_IMAGE_NS_BUF_SIZE, \
109 MT_RW_DATA | MT_NS | \
110 MT_USER, PAGE_SIZE)
111
112#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000)
113#define PLAT_SP_IMAGE_STACK_SIZE (32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE)
114#define PLAT_SP_IMAGE_STACK_BASE (PLAT_SQ_SP_HEAP_BASE + PLAT_SQ_SP_HEAP_SIZE)
115
116#define PLAT_SQ_SP_IMAGE_SIZE ULL(0x200000)
117#define PLAT_SQ_SP_IMAGE_MMAP MAP_REGION2(BL32_BASE, BL32_BASE, \
118 PLAT_SQ_SP_IMAGE_SIZE, \
119 MT_CODE | MT_SECURE | \
120 MT_USER, PAGE_SIZE)
121
122#define PLAT_SQ_SP_HEAP_BASE (BL32_BASE + PLAT_SQ_SP_IMAGE_SIZE)
123#define PLAT_SQ_SP_HEAP_SIZE ULL(0x800000)
124
125#define PLAT_SQ_SP_IMAGE_RW_MMAP MAP_REGION2(PLAT_SQ_SP_HEAP_BASE, \
126 PLAT_SQ_SP_HEAP_BASE, \
127 (PLAT_SQ_SP_HEAP_SIZE + \
128 PLAT_SP_IMAGE_STACK_SIZE), \
129 MT_RW_DATA | MT_SECURE | \
130 MT_USER, PAGE_SIZE)
131
132#define PLAT_SQ_SP_PRIV_BASE (PLAT_SP_IMAGE_STACK_BASE + \
133 PLAT_SP_IMAGE_STACK_SIZE)
134#define PLAT_SQ_SP_PRIV_SIZE ULL(0x40000)
135
136#define PLAT_SP_PRI 0x20
137#define PLAT_PRI_BITS 2
138#define PLAT_SPM_COOKIE_0 ULL(0)
139#define PLAT_SPM_COOKIE_1 ULL(0)
140
141/* Total number of memory regions with distinct properties */
142#define PLAT_SP_IMAGE_NUM_MEM_REGIONS 6
143
144#define PLAT_SP_IMAGE_MMAP_REGIONS 30
145#define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
146#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table"
Masahisa Kojima813b50b2020-06-02 05:54:13 +0900147#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "sp_xlat_table"
Ard Biesheuvelc0415c62018-12-29 19:44:35 +0100148
149#define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE
150#define PLAT_SQ_UART1_SIZE ULL(0x1000)
151#define PLAT_SQ_UART1_MMAP MAP_REGION_FLAT(PLAT_SQ_UART1_BASE, \
152 PLAT_SQ_UART1_SIZE, \
153 MT_DEVICE | MT_RW | \
154 MT_NS | MT_PRIVILEGED)
155
156#define PLAT_SQ_PERIPH_BASE 0x50000000
157#define PLAT_SQ_PERIPH_SIZE ULL(0x8000000)
158#define PLAT_SQ_PERIPH_MMAP MAP_REGION_FLAT(PLAT_SQ_PERIPH_BASE, \
159 PLAT_SQ_PERIPH_SIZE, \
160 MT_DEVICE | MT_RW | \
161 MT_NS | MT_USER)
162
163#define PLAT_SQ_FLASH_BASE 0x08000000
164#define PLAT_SQ_FLASH_SIZE ULL(0x8000000)
165#define PLAT_SQ_FLASH_MMAP MAP_REGION_FLAT(PLAT_SQ_FLASH_BASE, \
166 PLAT_SQ_FLASH_SIZE, \
167 MT_DEVICE | MT_RW | \
168 MT_NS | MT_USER)
169
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100170#endif /* PLATFORM_DEF_H */