blob: f5848a255ea912a2d62ab528a1fce7a9b7ba2cb3 [file] [log] [blame]
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01007#include <assert.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01008#include <errno.h>
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +01009#include <stdbool.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010010#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010011#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012
13#include <platform_def.h>
14
15#include <arch_helpers.h>
16#include <common/debug.h>
17#include <lib/utils_def.h>
18#include <lib/xlat_tables/xlat_tables_defs.h>
19#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010020
21#include "xlat_tables_private.h"
22
23#if LOG_LEVEL < LOG_LEVEL_VERBOSE
24
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010025void xlat_mmap_print(__unused const mmap_region_t *mmap)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010026{
27 /* Empty */
28}
29
30void xlat_tables_print(__unused xlat_ctx_t *ctx)
31{
32 /* Empty */
33}
34
35#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
36
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010037void xlat_mmap_print(const mmap_region_t *mmap)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010038{
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010039 printf("mmap:\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010040 const mmap_region_t *mm = mmap;
41
42 while (mm->size != 0U) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010043 printf(" VA:0x%lx PA:0x%llx size:0x%zx attr:0x%x granularity:0x%zx\n",
44 mm->base_va, mm->base_pa, mm->size, mm->attr,
45 mm->granularity);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010046 ++mm;
47 };
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010048 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010049}
50
51/* Print the attributes of the specified block descriptor. */
52static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
53{
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010054 uint64_t mem_type_index = ATTR_INDEX_GET(desc);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010055 int xlat_regime = ctx->xlat_regime;
56
57 if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010058 printf("MEM");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010059 } else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010060 printf("NC");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010061 } else {
62 assert(mem_type_index == ATTR_DEVICE_INDEX);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010063 printf("DEV");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010064 }
65
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010066 if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) {
67 /* For EL3 and EL2 only check the AP[2] and XN bits. */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010068 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
69 printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010070 } else {
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010071 assert(xlat_regime == EL1_EL0_REGIME);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010072 /*
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010073 * For EL0 and EL1:
74 * - In AArch64 PXN and UXN can be set independently but in
75 * AArch32 there is no UXN (XN affects both privilege levels).
76 * For consistency, we set them simultaneously in both cases.
77 * - RO and RW permissions must be the same in EL1 and EL0. If
78 * EL0 can access that memory region, so can EL1, with the
79 * same permissions.
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010080 */
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010081#if ENABLE_ASSERTIONS
82 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME);
83 uint64_t xn_perm = desc & xn_mask;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010084
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010085 assert((xn_perm == xn_mask) || (xn_perm == 0ULL));
86#endif
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010087 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010088 /* Only check one of PXN and UXN, the other one is the same. */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010089 printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010090 /*
91 * Privileged regions can only be accessed from EL1, user
92 * regions can be accessed from EL1 and EL0.
93 */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010094 printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010095 ? "-USER" : "-PRIV");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010096 }
97
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010098 printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010099}
100
101static const char * const level_spacers[] = {
102 "[LV0] ",
103 " [LV1] ",
104 " [LV2] ",
105 " [LV3] "
106};
107
108static const char *invalid_descriptors_ommited =
109 "%s(%d invalid descriptors omitted)\n";
110
111/*
112 * Recursive function that reads the translation tables passed as an argument
113 * and prints their status.
114 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100115static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
116 const uint64_t *table_base, unsigned int table_entries,
117 unsigned int level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100118{
119 assert(level <= XLAT_TABLE_LEVEL_MAX);
120
121 uint64_t desc;
122 uintptr_t table_idx_va = table_base_va;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100123 unsigned int table_idx = 0U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100124 size_t level_size = XLAT_BLOCK_SIZE(level);
125
126 /*
127 * Keep track of how many invalid descriptors are counted in a row.
128 * Whenever multiple invalid descriptors are found, only the first one
129 * is printed, and a line is added to inform about how many descriptors
130 * have been omitted.
131 */
132 int invalid_row_count = 0;
133
134 while (table_idx < table_entries) {
135
136 desc = table_base[table_idx];
137
138 if ((desc & DESC_MASK) == INVALID_DESC) {
139
140 if (invalid_row_count == 0) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100141 printf("%sVA:0x%lx size:0x%zx\n",
142 level_spacers[level],
143 table_idx_va, level_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100144 }
145 invalid_row_count++;
146
147 } else {
148
149 if (invalid_row_count > 1) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100150 printf(invalid_descriptors_ommited,
151 level_spacers[level],
152 invalid_row_count - 1);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100153 }
154 invalid_row_count = 0;
155
156 /*
157 * Check if this is a table or a block. Tables are only
158 * allowed in levels other than 3, but DESC_PAGE has the
159 * same value as DESC_TABLE, so we need to check.
160 */
161 if (((desc & DESC_MASK) == TABLE_DESC) &&
162 (level < XLAT_TABLE_LEVEL_MAX)) {
163 /*
164 * Do not print any PA for a table descriptor,
165 * as it doesn't directly map physical memory
166 * but instead points to the next translation
167 * table in the translation table walk.
168 */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100169 printf("%sVA:0x%lx size:0x%zx\n",
170 level_spacers[level],
171 table_idx_va, level_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100172
173 uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
174
175 xlat_tables_print_internal(ctx, table_idx_va,
176 (uint64_t *)addr_inner,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100177 XLAT_TABLE_ENTRIES, level + 1U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100178 } else {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100179 printf("%sVA:0x%lx PA:0x%llx size:0x%zx ",
180 level_spacers[level], table_idx_va,
181 (uint64_t)(desc & TABLE_ADDR_MASK),
182 level_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100183 xlat_desc_print(ctx, desc);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100184 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100185 }
186 }
187
188 table_idx++;
189 table_idx_va += level_size;
190 }
191
192 if (invalid_row_count > 1) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100193 printf(invalid_descriptors_ommited,
194 level_spacers[level], invalid_row_count - 1);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100195 }
196}
197
198void xlat_tables_print(xlat_ctx_t *ctx)
199{
200 const char *xlat_regime_str;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100201 int used_page_tables;
202
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100203 if (ctx->xlat_regime == EL1_EL0_REGIME) {
204 xlat_regime_str = "1&0";
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100205 } else if (ctx->xlat_regime == EL2_REGIME) {
206 xlat_regime_str = "2";
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100207 } else {
208 assert(ctx->xlat_regime == EL3_REGIME);
209 xlat_regime_str = "3";
210 }
211 VERBOSE("Translation tables state:\n");
212 VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
213 VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100214 VERBOSE(" Max allowed VA: 0x%lx\n", ctx->va_max_address);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100215 VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100216 VERBOSE(" Max mapped VA: 0x%lx\n", ctx->max_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100217
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100218 VERBOSE(" Initial lookup level: %u\n", ctx->base_level);
219 VERBOSE(" Entries @initial lookup level: %u\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100220 ctx->base_table_entries);
221
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100222#if PLAT_XLAT_TABLES_DYNAMIC
223 used_page_tables = 0;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100224 for (int i = 0; i < ctx->tables_num; ++i) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100225 if (ctx->tables_mapped_regions[i] != 0)
226 ++used_page_tables;
227 }
228#else
229 used_page_tables = ctx->next_table;
230#endif
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100231 VERBOSE(" Used %d sub-tables out of %d (spare: %d)\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100232 used_page_tables, ctx->tables_num,
233 ctx->tables_num - used_page_tables);
234
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100235 xlat_tables_print_internal(ctx, 0U, ctx->base_table,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100236 ctx->base_table_entries, ctx->base_level);
237}
238
239#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
240
241/*
242 * Do a translation table walk to find the block or page descriptor that maps
243 * virtual_addr.
244 *
245 * On success, return the address of the descriptor within the translation
246 * table. Its lookup level is stored in '*out_level'.
247 * On error, return NULL.
248 *
249 * xlat_table_base
250 * Base address for the initial lookup level.
251 * xlat_table_base_entries
252 * Number of entries in the translation table for the initial lookup level.
253 * virt_addr_space_size
254 * Size in bytes of the virtual address space.
255 */
256static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr,
257 void *xlat_table_base,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100258 unsigned int xlat_table_base_entries,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100259 unsigned long long virt_addr_space_size,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100260 unsigned int *out_level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100261{
262 unsigned int start_level;
263 uint64_t *table;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100264 unsigned int entries;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100265
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100266 start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100267
268 table = xlat_table_base;
269 entries = xlat_table_base_entries;
270
271 for (unsigned int level = start_level;
272 level <= XLAT_TABLE_LEVEL_MAX;
273 ++level) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100274 uint64_t idx, desc, desc_type;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100275
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100276 idx = XLAT_TABLE_IDX(virtual_addr, level);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100277 if (idx >= entries) {
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100278 WARN("Missing xlat table entry at address 0x%lx\n",
279 virtual_addr);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100280 return NULL;
281 }
282
283 desc = table[idx];
284 desc_type = desc & DESC_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100285
286 if (desc_type == INVALID_DESC) {
287 VERBOSE("Invalid entry (memory not mapped)\n");
288 return NULL;
289 }
290
291 if (level == XLAT_TABLE_LEVEL_MAX) {
292 /*
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100293 * Only page descriptors allowed at the final lookup
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100294 * level.
295 */
296 assert(desc_type == PAGE_DESC);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100297 *out_level = level;
298 return &table[idx];
299 }
300
301 if (desc_type == BLOCK_DESC) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100302 *out_level = level;
303 return &table[idx];
304 }
305
306 assert(desc_type == TABLE_DESC);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100307 table = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK);
308 entries = XLAT_TABLE_ENTRIES;
309 }
310
311 /*
312 * This shouldn't be reached, the translation table walk should end at
313 * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop.
314 */
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100315 assert(false);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100316
317 return NULL;
318}
319
320
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100321static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx,
322 uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100323 unsigned long long *addr_pa, unsigned int *table_level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100324{
325 uint64_t *entry;
326 uint64_t desc;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100327 unsigned int level;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100328 unsigned long long virt_addr_space_size;
329
330 /*
331 * Sanity-check arguments.
332 */
333 assert(ctx != NULL);
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100334 assert(ctx->initialized);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100335 assert((ctx->xlat_regime == EL1_EL0_REGIME) ||
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100336 (ctx->xlat_regime == EL2_REGIME) ||
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100337 (ctx->xlat_regime == EL3_REGIME));
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100338
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100339 virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1ULL;
340 assert(virt_addr_space_size > 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100341
342 entry = find_xlat_table_entry(base_va,
343 ctx->base_table,
344 ctx->base_table_entries,
345 virt_addr_space_size,
346 &level);
347 if (entry == NULL) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100348 WARN("Address 0x%lx is not mapped.\n", base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100349 return -EINVAL;
350 }
351
352 if (addr_pa != NULL) {
353 *addr_pa = *entry & TABLE_ADDR_MASK;
354 }
355
356 if (table_entry != NULL) {
357 *table_entry = entry;
358 }
359
360 if (table_level != NULL) {
361 *table_level = level;
362 }
363
364 desc = *entry;
365
366#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
367 VERBOSE("Attributes: ");
368 xlat_desc_print(ctx, desc);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100369 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100370#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
371
372 assert(attributes != NULL);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100373 *attributes = 0U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100374
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100375 uint64_t attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100376
377 if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
378 *attributes |= MT_MEMORY;
379 } else if (attr_index == ATTR_NON_CACHEABLE_INDEX) {
380 *attributes |= MT_NON_CACHEABLE;
381 } else {
382 assert(attr_index == ATTR_DEVICE_INDEX);
383 *attributes |= MT_DEVICE;
384 }
385
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100386 uint64_t ap2_bit = (desc >> AP2_SHIFT) & 1U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100387
388 if (ap2_bit == AP2_RW)
389 *attributes |= MT_RW;
390
391 if (ctx->xlat_regime == EL1_EL0_REGIME) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100392 uint64_t ap1_bit = (desc >> AP1_SHIFT) & 1U;
393
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100394 if (ap1_bit == AP1_ACCESS_UNPRIVILEGED)
395 *attributes |= MT_USER;
396 }
397
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100398 uint64_t ns_bit = (desc >> NS_SHIFT) & 1U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100399
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100400 if (ns_bit == 1U)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100401 *attributes |= MT_NS;
402
403 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
404
405 if ((desc & xn_mask) == xn_mask) {
406 *attributes |= MT_EXECUTE_NEVER;
407 } else {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100408 assert((desc & xn_mask) == 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100409 }
410
411 return 0;
412}
413
414
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100415int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
416 uint32_t *attr)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100417{
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100418 return xlat_get_mem_attributes_internal(ctx, base_va, attr,
419 NULL, NULL, NULL);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100420}
421
422
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100423int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
424 size_t size, uint32_t attr)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100425{
426 /* Note: This implementation isn't optimized. */
427
428 assert(ctx != NULL);
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100429 assert(ctx->initialized);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100430
431 unsigned long long virt_addr_space_size =
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100432 (unsigned long long)ctx->va_max_address + 1U;
433 assert(virt_addr_space_size > 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100434
435 if (!IS_PAGE_ALIGNED(base_va)) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100436 WARN("%s: Address 0x%lx is not aligned on a page boundary.\n",
437 __func__, base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100438 return -EINVAL;
439 }
440
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100441 if (size == 0U) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100442 WARN("%s: Size is 0.\n", __func__);
443 return -EINVAL;
444 }
445
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100446 if ((size % PAGE_SIZE) != 0U) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100447 WARN("%s: Size 0x%zx is not a multiple of a page size.\n",
448 __func__, size);
449 return -EINVAL;
450 }
451
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100452 if (((attr & MT_EXECUTE_NEVER) == 0U) && ((attr & MT_RW) != 0U)) {
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100453 WARN("%s: Mapping memory as read-write and executable not allowed.\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100454 __func__);
455 return -EINVAL;
456 }
457
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100458 size_t pages_count = size / PAGE_SIZE;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100459
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100460 VERBOSE("Changing memory attributes of %zu pages starting from address 0x%lx...\n",
461 pages_count, base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100462
463 uintptr_t base_va_original = base_va;
464
465 /*
466 * Sanity checks.
467 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100468 for (size_t i = 0U; i < pages_count; ++i) {
469 const uint64_t *entry;
470 uint64_t desc, attr_index;
471 unsigned int level;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100472
473 entry = find_xlat_table_entry(base_va,
474 ctx->base_table,
475 ctx->base_table_entries,
476 virt_addr_space_size,
477 &level);
478 if (entry == NULL) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100479 WARN("Address 0x%lx is not mapped.\n", base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100480 return -EINVAL;
481 }
482
483 desc = *entry;
484
485 /*
486 * Check that all the required pages are mapped at page
487 * granularity.
488 */
489 if (((desc & DESC_MASK) != PAGE_DESC) ||
490 (level != XLAT_TABLE_LEVEL_MAX)) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100491 WARN("Address 0x%lx is not mapped at the right granularity.\n",
492 base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100493 WARN("Granularity is 0x%llx, should be 0x%x.\n",
494 (unsigned long long)XLAT_BLOCK_SIZE(level), PAGE_SIZE);
495 return -EINVAL;
496 }
497
498 /*
499 * If the region type is device, it shouldn't be executable.
500 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100501 attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100502 if (attr_index == ATTR_DEVICE_INDEX) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100503 if ((attr & MT_EXECUTE_NEVER) == 0U) {
504 WARN("Setting device memory as executable at address 0x%lx.",
505 base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100506 return -EINVAL;
507 }
508 }
509
510 base_va += PAGE_SIZE;
511 }
512
513 /* Restore original value. */
514 base_va = base_va_original;
515
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100516 for (unsigned int i = 0U; i < pages_count; ++i) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100517
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100518 uint32_t old_attr = 0U, new_attr;
519 uint64_t *entry = NULL;
520 unsigned int level = 0U;
521 unsigned long long addr_pa = 0ULL;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100522
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100523 (void) xlat_get_mem_attributes_internal(ctx, base_va, &old_attr,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100524 &entry, &addr_pa, &level);
525
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100526 /*
527 * From attr, only MT_RO/MT_RW, MT_EXECUTE/MT_EXECUTE_NEVER and
528 * MT_USER/MT_PRIVILEGED are taken into account. Any other
529 * information is ignored.
530 */
531
532 /* Clean the old attributes so that they can be rebuilt. */
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100533 new_attr = old_attr & ~(MT_RW | MT_EXECUTE_NEVER | MT_USER);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100534
535 /*
536 * Update attributes, but filter out the ones this function
537 * isn't allowed to change.
538 */
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100539 new_attr |= attr & (MT_RW | MT_EXECUTE_NEVER | MT_USER);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100540
541 /*
542 * The break-before-make sequence requires writing an invalid
543 * descriptor and making sure that the system sees the change
544 * before writing the new descriptor.
545 */
546 *entry = INVALID_DESC;
Antonio Nino Diaz37a5efa2018-08-07 12:47:12 +0100547#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
548 dccvac((uintptr_t)entry);
549#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100550 /* Invalidate any cached copy of this mapping in the TLBs. */
Antonio Nino Diazad5dc7f2018-07-11 09:46:45 +0100551 xlat_arch_tlbi_va(base_va, ctx->xlat_regime);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100552
553 /* Ensure completion of the invalidation. */
554 xlat_arch_tlbi_va_sync();
555
556 /* Write new descriptor */
557 *entry = xlat_desc(ctx, new_attr, addr_pa, level);
Antonio Nino Diaz37a5efa2018-08-07 12:47:12 +0100558#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
559 dccvac((uintptr_t)entry);
560#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100561 base_va += PAGE_SIZE;
562 }
563
564 /* Ensure that the last descriptor writen is seen by the system. */
565 dsbish();
566
567 return 0;
568}