blob: a5f58584d0b9af89c05b85c4cc86d5f937de730d [file] [log] [blame]
Saurabh Gorecha70389ca2020-04-22 21:31:24 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <assert.h>
9
10#include <bl31/bl31.h>
11#include <common/debug.h>
12#include <common/desc_image_load.h>
13#include <drivers/console.h>
14#include <drivers/generic_delay_timer.h>
15#include <lib/bl_aux_params/bl_aux_params.h>
16#include <lib/coreboot.h>
17#include <lib/spinlock.h>
18
19#include <platform.h>
20#include <qti_interrupt_svc.h>
21#include <qti_plat.h>
22#include <qti_uart_console.h>
23#include <qtiseclib_interface.h>
24
25/*
26 * Placeholder variables for copying the arguments that have been passed to
27 * BL31 from BL2.
28 */
29static entry_point_info_t bl33_image_ep_info;
30
31/*
32 * Variable to hold counter frequency for the CPU's generic timer. In this
33 * platform coreboot image configure counter frequency for boot core before
34 * reaching TF-A.
35 */
36static uint64_t g_qti_cpu_cntfrq;
37
38/*
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053039 * Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
40 * Any other value means cold booted.
41 */
Saurabh Gorechab8493012022-04-05 00:11:52 +053042uint32_t g_qti_bl31_cold_booted;
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053043
44/*******************************************************************************
45 * Perform any BL31 early platform setup common to ARM standard platforms.
46 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
47 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
48 * done before the MMU is initialized so that the memory layout can be used
49 * while creating page tables. BL2 has flushed this information to memory, so
50 * we are guaranteed to pick up good data.
51 ******************************************************************************/
52void bl31_early_platform_setup(u_register_t from_bl2,
53 u_register_t plat_params_from_bl2)
54{
55
56 g_qti_cpu_cntfrq = read_cntfrq_el0();
57
58 bl_aux_params_parse(plat_params_from_bl2, NULL);
59
60#if COREBOOT
61 if (coreboot_serial.baseaddr != 0) {
62 static console_t g_qti_console_uart;
63
64 qti_console_uart_register(&g_qti_console_uart,
65 coreboot_serial.baseaddr);
66 }
67#endif
68
69 /*
70 * Tell BL31 where the non-trusted software image
71 * is located and the entry state information
72 */
73 bl31_params_parse_helper(from_bl2, NULL, &bl33_image_ep_info);
74}
75
76void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
77 u_register_t arg2, u_register_t arg3)
78{
79 bl31_early_platform_setup(arg0, arg1);
80}
81
82/*******************************************************************************
83 * Perform the very early platform specific architectural setup here. At the
Elyes Haouas2be03c02023-02-13 09:14:48 +010084 * moment this only initializes the mmu in a quick and dirty way.
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053085 ******************************************************************************/
86void bl31_plat_arch_setup(void)
87{
Saurabh Gorechab8493012022-04-05 00:11:52 +053088 qti_setup_page_tables(
89 BL31_START,
90 BL31_END-BL31_START,
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053091 BL_CODE_BASE,
92 BL_CODE_END,
93 BL_RO_DATA_BASE,
Saurabh Gorechab8493012022-04-05 00:11:52 +053094 BL_RO_DATA_END
95 );
Saurabh Gorecha70389ca2020-04-22 21:31:24 +053096 enable_mmu_el3(0);
97}
98
99/*******************************************************************************
100 * Perform any BL31 platform setup common to ARM standard platforms
101 ******************************************************************************/
102void bl31_platform_setup(void)
103{
104 generic_delay_timer_init();
105 /* Initialize the GIC driver, CPU and distributor interfaces */
106 plat_qti_gic_driver_init();
107 plat_qti_gic_init();
108 qti_interrupt_svc_init();
109 qtiseclib_bl31_platform_setup();
110
111 /* set boot state to cold boot complete. */
112 g_qti_bl31_cold_booted = 0x1;
113}
114
115/*******************************************************************************
116 * Return a pointer to the 'entry_point_info' structure of the next image for the
117 * security state specified. BL33 corresponds to the non-secure image type
118 * while BL32 corresponds to the secure image type. A NULL pointer is returned
119 * if the image does not exist.
120 ******************************************************************************/
121entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
122{
123 /* QTI platform don't have BL32 implementation. */
124 assert(type == NON_SECURE);
125 assert(bl33_image_ep_info.h.type == PARAM_EP);
126 assert(bl33_image_ep_info.h.attr == NON_SECURE);
127 /*
128 * None of the images on the platforms can have 0x0
129 * as the entrypoint.
130 */
131 if (bl33_image_ep_info.pc) {
132 return &bl33_image_ep_info;
133 } else {
134 return NULL;
135 }
136}
137
138/*******************************************************************************
139 * This function is used by the architecture setup code to retrieve the counter
140 * frequency for the CPU's generic timer. This value will be programmed into the
141 * CNTFRQ_EL0 register. In Arm standard platforms, it returns the base frequency
142 * of the system counter, which is retrieved from the first entry in the
143 * frequency modes table. This will be used later in warm boot (psci_arch_setup)
144 * of CPUs to set when CPU frequency.
145 ******************************************************************************/
146unsigned int plat_get_syscnt_freq2(void)
147{
148 assert(g_qti_cpu_cntfrq != 0);
149 return g_qti_cpu_cntfrq;
150}