| Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | #include <plat/common/common_def.h> |
| 13 | |
| 14 | #include "../stm32mp2_def.h" |
| 15 | |
| 16 | /******************************************************************************* |
| 17 | * Generic platform constants |
| 18 | ******************************************************************************/ |
| 19 | |
| 20 | /* Size of cacheable stacks */ |
| 21 | #define PLATFORM_STACK_SIZE 0xC00 |
| 22 | |
| 23 | #define STM32MP_PRIMARY_CPU U(0x0) |
| 24 | #define STM32MP_SECONDARY_CPU U(0x1) |
| 25 | |
| 26 | #define MAX_IO_DEVICES U(4) |
| 27 | #define MAX_IO_HANDLES U(4) |
| 28 | #define MAX_IO_BLOCK_DEVICES U(1) |
| 29 | #define MAX_IO_MTD_DEVICES U(1) |
| 30 | |
| 31 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 32 | #define PLATFORM_CORE_COUNT U(2) |
| 33 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) |
| 34 | |
| 35 | #define PLAT_MAX_PWR_LVL U(5) |
| 36 | #define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5) |
| 37 | #define PLAT_NUM_PWR_DOMAINS U(7) |
| 38 | |
| 39 | /* Local power state for power domains in Run state. */ |
| 40 | #define STM32MP_LOCAL_STATE_RUN U(0) |
| 41 | /* Local power state for retention. */ |
| 42 | #define STM32MP_LOCAL_STATE_RET U(1) |
| 43 | #define STM32MP_LOCAL_STATE_LP U(2) |
| 44 | #define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP |
| 45 | /* Local power state for OFF/power-down. */ |
| 46 | #define STM32MP_LOCAL_STATE_OFF U(3) |
| 47 | #define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF |
| 48 | |
| 49 | /* Macros to parse the state information from State-ID (recommended encoding) */ |
| 50 | #define PLAT_LOCAL_PSTATE_WIDTH U(4) |
| 51 | #define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0) |
| 52 | |
| 53 | /******************************************************************************* |
| 54 | * BL2 specific defines. |
| 55 | ******************************************************************************/ |
| 56 | /* |
| 57 | * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug |
| 58 | * size plus a little space for growth. |
| 59 | */ |
| 60 | #define BL2_BASE STM32MP_BL2_BASE |
| 61 | #define BL2_LIMIT (STM32MP_BL2_BASE + \ |
| 62 | STM32MP_BL2_SIZE) |
| 63 | |
| 64 | /******************************************************************************* |
| 65 | * BL33 specific defines. |
| 66 | ******************************************************************************/ |
| 67 | #define BL33_BASE STM32MP_BL33_BASE |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * Platform specific page table and MMU setup constants |
| 71 | ******************************************************************************/ |
| 72 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33) |
| 73 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33) |
| 74 | |
| 75 | /******************************************************************************* |
| 76 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 77 | * aligned on the biggest cache line size in the platform. This is known only |
| 78 | * to the platform as it might have a combination of integrated and external |
| 79 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 80 | * line at any cache level. They could belong to different cpus/clusters & |
| 81 | * get written while being protected by different locks causing corruption of |
| 82 | * a valid mailbox address. |
| 83 | ******************************************************************************/ |
| 84 | #define CACHE_WRITEBACK_SHIFT 6 |
| 85 | #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) |
| 86 | |
| 87 | #endif /* PLATFORM_DEF_H */ |