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git01.mediatek.com / filogic / atf / 16d31089daa0b99a6bb37b60b9df66c10c6301ab / . / plat / arm / board / fvp_r / fvp_r_bl1_entrypoint.S
blob: 15f4c4349181231ffdead721b62f252bcae5410d [file] [log] [blame]
Gary Morrison3d7f6542021-01-27 13:08:47 -0600[diff] [blame]1/*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600[diff] [blame]8#include <asm_macros.S>
9#include <common/bl_common.h>
Gary Morrison3d7f6542021-01-27 13:08:47 -0600[diff] [blame]10#include <el2_common_macros.S>
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600[diff] [blame]11#include <lib/xlat_mpu/xlat_mpu.h>
Gary Morrison3d7f6542021-01-27 13:08:47 -0600[diff] [blame]12
13 .globl bl1_entrypoint
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600[diff] [blame]14 .globl bl1_run_next_image
Gary Morrison3d7f6542021-01-27 13:08:47 -0600[diff] [blame]15
16
17 /* -----------------------------------------------------
18 * bl1_entrypoint() is the entry point into the trusted
19 * firmware code when a cpu is released from warm or
20 * cold reset.
21 * -----------------------------------------------------
22 */
23
24func bl1_entrypoint
25 /* ---------------------------------------------------------------------
26 * If the reset address is programmable then bl1_entrypoint() is
27 * executed only on the cold boot path. Therefore, we can skip the warm
28 * boot mailbox mechanism.
29 * ---------------------------------------------------------------------
30 */
31 el2_entrypoint_common \
32 _init_sctlr=1 \
33 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
34 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
35 _init_memory=1 \
36 _init_c_runtime=1 \
37 _exception_vectors=bl1_exceptions \
38 _pie_fixup_size=0
39
40 /* --------------------------------------------------------------------
41 * Perform BL1 setup
42 * --------------------------------------------------------------------
43 */
44 bl bl1_setup
45
Gary Morrison3d7f6542021-01-27 13:08:47 -0600[diff] [blame]46 /* --------------------------------------------------------------------
47 * Initialize platform and jump to our c-entry point
48 * for this type of reset.
49 * --------------------------------------------------------------------
50 */
51 bl bl1_main
52
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600[diff] [blame]53 /* ---------------------------------------------
54 * Should never reach this point.
55 * ---------------------------------------------
56 */
57 no_ret plat_panic_handler
58endfunc bl1_entrypoint
59
60func bl1_run_next_image
61 mov x20,x0
62
63 /* ---------------------------------------------
64 * MPU needs to be disabled because both BL1 and BL33 execute
65 * in EL2, and therefore share the same address space.
66 * BL33 will initialize the address space according to its
67 * own requirement.
68 * ---------------------------------------------
69 */
70 bl disable_mpu_icache_el2
71
72 /* ---------------------------------------------
73 * Wipe clean and disable all MPU regions. This function expects
74 * that the MPU has already been turned off, and caching concerns
75 * addressed, but it also explicitly turns off the MPU.
76 * ---------------------------------------------
77 */
78 bl clear_all_mpu_regions
79
Gary Morrison3d7f6542021-01-27 13:08:47 -0600[diff] [blame]80 /* --------------------------------------------------
81 * Do the transition to next boot image.
82 * --------------------------------------------------
83 */
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600[diff] [blame]84 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
85 msr elr_el2, x0
86 msr spsr_el2, x1
87
88 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
89 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
90 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
91 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
92 exception_return
93endfunc bl1_run_next_image