Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_FCS_H |
| 8 | #define SOCFPGA_FCS_H |
| 9 | |
| 10 | /* FCS Definitions */ |
| 11 | |
| 12 | #define FCS_RANDOM_WORD_SIZE 8U |
| 13 | #define FCS_PROV_DATA_WORD_SIZE 44U |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 14 | #define FCS_SHA384_WORD_SIZE 12U |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 15 | |
| 16 | #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) |
| 17 | #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 18 | #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 19 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 20 | #define FCS_MODE_DECRYPT 0x0 |
| 21 | #define FCS_MODE_ENCRYPT 0x1 |
| 22 | #define FCS_ENCRYPTION_DATA_0 0x10100 |
| 23 | #define FCS_DECRYPTION_DATA_0 0x10102 |
| 24 | #define FCS_OWNER_ID_OFFSET 0xC |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 25 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 26 | #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 |
| 27 | #define PSGSIGMA_SESSION_ID_ONE 0x1 |
| 28 | #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF |
| 29 | |
| 30 | #define RESERVED_AS_ZERO 0x0 |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 31 | /* FCS Single cert */ |
| 32 | |
| 33 | #define FCS_BIG_CNTR_SEL 0x1 |
| 34 | |
| 35 | #define FCS_SVN_CNTR_0_SEL 0x2 |
| 36 | #define FCS_SVN_CNTR_1_SEL 0x3 |
| 37 | #define FCS_SVN_CNTR_2_SEL 0x4 |
| 38 | #define FCS_SVN_CNTR_3_SEL 0x5 |
| 39 | |
| 40 | #define FCS_BIG_CNTR_VAL_MAX 495U |
| 41 | #define FCS_SVN_CNTR_VAL_MAX 64U |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 42 | |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame^] | 43 | /* FCS Attestation Cert Request Parameter */ |
| 44 | |
| 45 | #define FCS_ALIAS_CERT 0x01 |
| 46 | #define FCS_DEV_ID_SELF_SIGN_CERT 0x02 |
| 47 | #define FCS_DEV_ID_ENROLL_CERT 0x04 |
| 48 | #define FCS_ENROLL_SELF_SIGN_CERT 0x08 |
| 49 | #define FCS_PLAT_KEY_CERT 0x10 |
| 50 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 51 | /* FCS Payload Structure */ |
| 52 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 53 | typedef struct fcs_encrypt_payload_t { |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 54 | uint32_t first_word; |
| 55 | uint32_t src_addr; |
| 56 | uint32_t src_size; |
| 57 | uint32_t dst_addr; |
| 58 | uint32_t dst_size; |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 59 | } fcs_encrypt_payload; |
| 60 | |
| 61 | typedef struct fcs_decrypt_payload_t { |
| 62 | uint32_t first_word; |
| 63 | uint32_t owner_id[2]; |
| 64 | uint32_t src_addr; |
| 65 | uint32_t src_size; |
| 66 | uint32_t dst_addr; |
| 67 | uint32_t dst_size; |
| 68 | } fcs_decrypt_payload; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 69 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 70 | typedef struct psgsigma_teardown_msg_t { |
| 71 | uint32_t reserved_word; |
| 72 | uint32_t magic_word; |
| 73 | uint32_t session_id; |
| 74 | } psgsigma_teardown_msg; |
| 75 | |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 76 | typedef struct fcs_cntr_set_preauth_payload_t { |
| 77 | uint32_t first_word; |
| 78 | uint32_t counter_value; |
| 79 | } fcs_cntr_set_preauth_payload; |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 80 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 81 | /* Functions Definitions */ |
| 82 | |
| 83 | uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, |
| 84 | uint32_t *mbox_error); |
| 85 | uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, |
| 86 | uint32_t *send_id); |
| 87 | uint32_t intel_fcs_get_provision_data(uint32_t *send_id); |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 88 | uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, |
| 89 | int32_t counter_value, |
| 90 | uint32_t test_bit, |
| 91 | uint32_t *mbox_error); |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 92 | uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, |
| 93 | uint32_t dst_addr, uint32_t dst_size, |
| 94 | uint32_t *send_id); |
| 95 | |
| 96 | uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, |
| 97 | uint32_t dst_addr, uint32_t dst_size, |
| 98 | uint32_t *send_id); |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 99 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 100 | int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); |
| 101 | int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); |
| 102 | int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, |
| 103 | uint64_t dst_addr, uint32_t *dst_size, |
| 104 | uint32_t *mbox_error); |
| 105 | int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, |
| 106 | uint64_t dst_addr, uint32_t *dst_size, |
| 107 | uint32_t *mbox_error); |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 108 | uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, |
| 109 | uint32_t *mbox_error); |
| 110 | |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame^] | 111 | int intel_fcs_create_cert_on_reload(uint32_t cert_request, |
| 112 | uint32_t *mbox_error); |
| 113 | int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, |
| 114 | uint32_t *dst_size, uint32_t *mbox_error); |
| 115 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 116 | #endif /* SOCFPGA_FCS_H */ |