Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | # |
Varun Wadekar | ed3c62b | 2017-03-06 09:15:15 -0800 | [diff] [blame] | 2 | # Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | # |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | # SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | # |
| 6 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 7 | SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC} |
| 8 | |
Varun Wadekar | a441f72 | 2017-04-26 13:46:11 -0700 | [diff] [blame] | 9 | # dump the state on crash console |
| 10 | CRASH_REPORTING := 1 |
| 11 | $(eval $(call add_define,CRASH_REPORTING)) |
Varun Wadekar | 6077dce | 2016-01-27 11:31:06 -0800 | [diff] [blame] | 12 | |
Varun Wadekar | 38c8022 | 2017-04-26 13:48:19 -0700 | [diff] [blame] | 13 | # enable assert() for release/debug builds |
| 14 | ENABLE_ASSERTIONS := 1 |
Varun Wadekar | 96658a9 | 2017-08-03 11:38:32 -0700 | [diff] [blame] | 15 | PLAT_LOG_LEVEL_ASSERT := 40 |
| 16 | $(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT)) |
Varun Wadekar | 38c8022 | 2017-04-26 13:48:19 -0700 | [diff] [blame] | 17 | |
Varun Wadekar | a441f72 | 2017-04-26 13:46:11 -0700 | [diff] [blame] | 18 | # enable dynamic memory mapping |
| 19 | PLAT_XLAT_TABLES_DYNAMIC := 1 |
| 20 | $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) |
| 21 | |
| 22 | # Enable PSCI v1.0 extended state ID format |
| 23 | PSCI_EXTENDED_STATE_ID := 1 |
| 24 | |
| 25 | # code and read-only data should be put on separate memory pages |
| 26 | SEPARATE_CODE_AND_RODATA := 1 |
| 27 | |
| 28 | # do not use coherent memory |
| 29 | USE_COHERENT_MEM := 0 |
| 30 | |
David Cunado | c5b0c0f | 2017-10-31 23:19:21 +0000 | [diff] [blame] | 31 | # do not enable SVE |
| 32 | ENABLE_SVE_FOR_NS := 0 |
| 33 | |
Varun Wadekar | e0ecdd0 | 2017-08-03 17:17:00 -0700 | [diff] [blame] | 34 | # enable D-cache early during CPU warmboot |
| 35 | WARMBOOT_ENABLE_DCACHE_EARLY := 1 |
| 36 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 37 | include plat/nvidia/tegra/common/tegra_common.mk |
| 38 | include ${SOC_DIR}/platform_${TARGET_SOC}.mk |
Varun Wadekar | c39b0ba | 2015-07-21 10:16:13 +0530 | [diff] [blame] | 39 | |
| 40 | # modify BUILD_PLAT to point to SoC specific build directory |
| 41 | BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE} |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 42 | |
Varun Wadekar | 7919a60 | 2017-09-06 17:17:12 -0700 | [diff] [blame] | 43 | # platform cflags (enable signed comparisons, disable stdlib) |
| 44 | TF_CFLAGS += -Wsign-compare -nostdlib |