Saurabh Gorecha | 70389ca | 2020-04-22 21:31:24 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <assert.h> |
| 9 | #include <errno.h> |
| 10 | #include <stdbool.h> |
| 11 | #include <stdint.h> |
| 12 | |
| 13 | #include <common/debug.h> |
| 14 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 15 | |
| 16 | #include <platform_def.h> |
| 17 | #include <qti_plat.h> |
| 18 | #include <qtiseclib_interface.h> |
| 19 | |
| 20 | /* |
| 21 | * Table of regions for various BL stages to map using the MMU. |
| 22 | * This doesn't include TZRAM as the 'mem_layout' argument passed to |
| 23 | * qti_configure_mmu_elx() will give the available subset of that, |
| 24 | */ |
| 25 | |
| 26 | const mmap_region_t plat_qti_mmap[] = { |
| 27 | MAP_REGION_FLAT(QTI_DEVICE_BASE, QTI_DEVICE_SIZE, |
| 28 | MT_DEVICE | MT_RW | MT_SECURE), |
| 29 | MAP_REGION_FLAT(QTI_AOP_CMD_DB_BASE, QTI_AOP_CMD_DB_SIZE, |
| 30 | MT_NS | MT_RO | MT_EXECUTE_NEVER), |
| 31 | {0} |
| 32 | }; |
| 33 | |
| 34 | CASSERT(ARRAY_SIZE(plat_qti_mmap) <= MAX_MMAP_REGIONS, assert_max_mmap_regions); |
| 35 | |
| 36 | |
| 37 | bool qti_is_overlap_atf_rg(unsigned long long addr, size_t size) |
| 38 | { |
| 39 | if (addr > addr + size |
| 40 | || (BL31_BASE < addr + size && BL31_LIMIT > addr)) { |
| 41 | return true; |
| 42 | } |
| 43 | return false; |
| 44 | } |
| 45 | |
| 46 | /* |
| 47 | * unsigned int plat_qti_my_cluster_pos(void) |
| 48 | * definition to get the cluster index of the calling CPU. |
| 49 | * - In ARM v8 (MPIDR_EL1[24]=0) |
| 50 | * ClusterId = MPIDR_EL1[15:8] |
| 51 | * - In ARM v8.1 & Later version (MPIDR_EL1[24]=1) |
| 52 | * ClusterId = MPIDR_EL1[23:15] |
| 53 | */ |
| 54 | unsigned int plat_qti_my_cluster_pos(void) |
| 55 | { |
| 56 | unsigned int mpidr, cluster_id; |
| 57 | |
| 58 | mpidr = read_mpidr_el1(); |
| 59 | if ((mpidr & MPIDR_MT_MASK) == 0) { /* MT not supported */ |
| 60 | cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 61 | } else { /* MT supported */ |
| 62 | cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; |
| 63 | } |
| 64 | assert(cluster_id < PLAT_CLUSTER_COUNT); |
| 65 | return cluster_id; |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Set up the page tables for the generic and platform-specific memory regions. |
| 70 | * The extents of the generic memory regions are specified by the function |
| 71 | * arguments and consist of: |
| 72 | * - Trusted SRAM seen by the BL image; |
| 73 | * - Code section; |
| 74 | * - Read-only data section; |
| 75 | * - Coherent memory region, if applicable. |
| 76 | */ |
| 77 | void qti_setup_page_tables(uintptr_t total_base, |
| 78 | size_t total_size, |
| 79 | uintptr_t code_start, |
| 80 | uintptr_t code_limit, |
| 81 | uintptr_t rodata_start, |
| 82 | uintptr_t rodata_limit, |
| 83 | uintptr_t coh_start, uintptr_t coh_limit) |
| 84 | { |
| 85 | /* |
| 86 | * Map the Trusted SRAM with appropriate memory attributes. |
| 87 | * Subsequent mappings will adjust the attributes for specific regions. |
| 88 | */ |
| 89 | VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", |
| 90 | (void *)total_base, (void *)(total_base + total_size)); |
| 91 | mmap_add_region(total_base, total_base, |
| 92 | total_size, MT_MEMORY | MT_RW | MT_SECURE); |
| 93 | |
| 94 | /* Re-map the code section */ |
| 95 | VERBOSE("Code region: %p - %p\n", |
| 96 | (void *)code_start, (void *)code_limit); |
| 97 | mmap_add_region(code_start, code_start, |
| 98 | code_limit - code_start, MT_CODE | MT_SECURE); |
| 99 | |
| 100 | /* Re-map the read-only data section */ |
| 101 | VERBOSE("Read-only data region: %p - %p\n", |
| 102 | (void *)rodata_start, (void *)rodata_limit); |
| 103 | mmap_add_region(rodata_start, rodata_start, |
| 104 | rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE); |
| 105 | |
| 106 | /* Re-map the coherent memory region */ |
| 107 | VERBOSE("Coherent region: %p - %p\n", |
| 108 | (void *)coh_start, (void *)coh_limit); |
| 109 | mmap_add_region(coh_start, coh_start, |
| 110 | coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE); |
| 111 | |
| 112 | /* Now (re-)map the platform-specific memory regions */ |
| 113 | mmap_add(plat_qti_mmap); |
| 114 | |
| 115 | /* Create the page tables to reflect the above mappings */ |
| 116 | init_xlat_tables(); |
| 117 | } |
| 118 | |
| 119 | static inline void qti_align_mem_region(uintptr_t addr, size_t size, |
| 120 | uintptr_t *aligned_addr, |
| 121 | size_t *aligned_size) |
| 122 | { |
| 123 | *aligned_addr = round_down(addr, PAGE_SIZE); |
| 124 | *aligned_size = round_up(addr - *aligned_addr + size, PAGE_SIZE); |
| 125 | } |
| 126 | |
| 127 | int qti_mmap_add_dynamic_region(uintptr_t base_pa, size_t size, |
| 128 | unsigned int attr) |
| 129 | { |
| 130 | uintptr_t aligned_pa; |
| 131 | size_t aligned_size; |
| 132 | |
| 133 | qti_align_mem_region(base_pa, size, &aligned_pa, &aligned_size); |
| 134 | |
| 135 | if (qti_is_overlap_atf_rg(base_pa, size)) { |
| 136 | /* Memory shouldn't overlap with TF-A range. */ |
| 137 | return -EPERM; |
| 138 | } |
| 139 | |
| 140 | return mmap_add_dynamic_region(aligned_pa, aligned_pa, aligned_size, |
| 141 | attr); |
| 142 | } |
| 143 | |
| 144 | int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size) |
| 145 | { |
| 146 | qti_align_mem_region(base_va, size, &base_va, &size); |
| 147 | return mmap_remove_dynamic_region(base_va, size); |
| 148 | } |