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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
Antonio Nino Diaz83d8c792018-08-17 14:25:08 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/tbbr/tbbr_img_def.h>
12#include <lib/utils_def.h>
13#include <plat/common/common_def.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000014
15#include "../rpi3_hw.h"
16
17/* Special value used to verify platform parameters from BL2 to BL31 */
18#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
19
20#define PLATFORM_STACK_SIZE ULL(0x1000)
21
22#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
23#define PLATFORM_CLUSTER_COUNT U(1)
24#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
25#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
26
27#define RPI3_PRIMARY_CPU U(0)
28
29#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
30#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
31 PLATFORM_CORE_COUNT)
32
33#define PLAT_MAX_RET_STATE U(1)
34#define PLAT_MAX_OFF_STATE U(2)
35
36/* Local power state for power domains in Run state. */
37#define PLAT_LOCAL_STATE_RUN U(0)
38/* Local power state for retention. Valid only for CPU power domains */
39#define PLAT_LOCAL_STATE_RET U(1)
40/*
41 * Local power state for OFF/power-down. Valid for CPU and cluster power
42 * domains.
43 */
44#define PLAT_LOCAL_STATE_OFF U(2)
45
46/*
47 * Macros used to parse state information from State-ID if it is using the
48 * recommended encoding for State-ID.
49 */
50#define PLAT_LOCAL_PSTATE_WIDTH U(4)
51#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
52
53/*
54 * Some data must be aligned on the biggest cache line size in the platform.
55 * This is known only to the platform as it might have a combination of
56 * integrated and external caches.
57 */
58#define CACHE_WRITEBACK_SHIFT U(6)
59#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
60
61/*
62 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
63 * secure DRAM. Note that this is all actually DRAM with different names,
64 * there is no Secure RAM in the Raspberry Pi 3.
65 */
Pete Batardf820cad2018-11-15 22:29:59 +000066#if RPI3_USE_UEFI_MAP
67#define SEC_ROM_BASE ULL(0x00000000)
68#define SEC_ROM_SIZE ULL(0x00010000)
69
70/* FIP placed after ROM to append it to BL1 with very little padding. */
71#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
72#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000)
73
74/* Reserve 2M of secure SRAM and DRAM, starting at 2M */
75#define SEC_SRAM_BASE ULL(0x00200000)
76#define SEC_SRAM_SIZE ULL(0x00100000)
77
78#define SEC_DRAM0_BASE ULL(0x00300000)
79#define SEC_DRAM0_SIZE ULL(0x00100000)
80
81/* Windows on ARM requires some RAM at 4M */
82#define NS_DRAM0_BASE ULL(0x00400000)
83#define NS_DRAM0_SIZE ULL(0x00C00000)
84#else
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000085#define SEC_ROM_BASE ULL(0x00000000)
Ying-Chun Liu (PaulLiu)9128df62018-07-04 02:26:48 +080086#define SEC_ROM_SIZE ULL(0x00020000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000087
88/* FIP placed after ROM to append it to BL1 with very little padding. */
Ying-Chun Liu (PaulLiu)9128df62018-07-04 02:26:48 +080089#define PLAT_RPI3_FIP_BASE ULL(0x00020000)
90#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000091
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +010092/* We have 16M of memory reserved starting at 256M */
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000093#define SEC_SRAM_BASE ULL(0x10000000)
94#define SEC_SRAM_SIZE ULL(0x00100000)
95
96#define SEC_DRAM0_BASE ULL(0x10100000)
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +010097#define SEC_DRAM0_SIZE ULL(0x00F00000)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000098/* End of reserved memory */
99
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +0100100#define NS_DRAM0_BASE ULL(0x11000000)
101#define NS_DRAM0_SIZE ULL(0x01000000)
Pete Batardf820cad2018-11-15 22:29:59 +0000102#endif /* RPI3_USE_UEFI_MAP */
Antonio Nino Diaz50c5a9e2018-07-15 11:56:33 +0100103
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000104/*
105 * BL33 entrypoint.
106 */
107#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE
108#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE
109
110/*
111 * I/O registers.
112 */
113#define DEVICE0_BASE RPI3_IO_BASE
114#define DEVICE0_SIZE RPI3_IO_SIZE
115
116/*
117 * Arm TF lives in SRAM, partition it here
118 */
119#define SHARED_RAM_BASE SEC_SRAM_BASE
120#define SHARED_RAM_SIZE ULL(0x00001000)
121
122#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
123#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
124
125/*
126 * Mailbox to control the secondary cores.All secondary cores are held in a wait
127 * loop in cold boot. To release them perform the following steps (plus any
128 * additional barriers that may be needed):
129 *
130 * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
131 * *entrypoint = ADDRESS_TO_JUMP_TO;
132 *
133 * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
134 * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
135 *
136 * sev();
137 */
138#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
139
Antonio Nino Diazbc297332018-07-14 01:22:43 +0100140/* The secure entry point to be used on warm reset by all CPUs. */
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000141#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE
142#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
143
Antonio Nino Diazbc297332018-07-14 01:22:43 +0100144/* Hold entries for each CPU. */
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000145#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \
146 PLAT_RPI3_TM_ENTRYPOINT_SIZE)
147#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
148#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
149 PLATFORM_CORE_COUNT)
150
151#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
152 PLAT_RPI3_TM_HOLD_SIZE)
153
154#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
155#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
156
157/*
158 * BL1 specific defines.
159 *
160 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
161 * addresses.
162 *
163 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
164 * the current BL1 RW debug size plus a little space for growth.
165 */
166#define PLAT_MAX_BL1_RW_SIZE ULL(0x12000)
167
168#define BL1_RO_BASE SEC_ROM_BASE
169#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
170#define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE)
171#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
172
173/*
174 * BL2 specific defines.
175 *
176 * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug
177 * size plus a little space for growth.
178 */
179#define PLAT_MAX_BL2_SIZE ULL(0x2C000)
180
181#define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE)
182#define BL2_LIMIT BL31_BASE
183
184/*
185 * BL31 specific defines.
186 *
187 * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
188 * current BL31 debug size plus a little space for growth.
189 */
190#define PLAT_MAX_BL31_SIZE ULL(0x20000)
191
192#define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE)
193#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
194#define BL31_PROGBITS_LIMIT BL1_RW_BASE
195
196/*
197 * BL32 specific defines.
198 *
199 * BL32 can execute from Secure SRAM or Secure DRAM.
200 */
201#define BL32_SRAM_BASE BL_RAM_BASE
202#define BL32_SRAM_LIMIT BL31_BASE
203#define BL32_DRAM_BASE SEC_DRAM0_BASE
204#define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE)
205
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800206#ifdef SPD_opteed
207/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
208#define RPI3_OPTEE_PAGEABLE_LOAD_SIZE 0x080000 /* 512KB */
209#define RPI3_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - \
210 RPI3_OPTEE_PAGEABLE_LOAD_SIZE)
211#endif
212
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000213#define SEC_SRAM_ID 0
214#define SEC_DRAM_ID 1
215
216#if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID
217# define BL32_MEM_BASE BL_RAM_BASE
218# define BL32_MEM_SIZE BL_RAM_SIZE
219# define BL32_BASE BL32_SRAM_BASE
220# define BL32_LIMIT BL32_SRAM_LIMIT
221#elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID
222# define BL32_MEM_BASE SEC_DRAM0_BASE
223# define BL32_MEM_SIZE SEC_DRAM0_SIZE
224# define BL32_BASE BL32_DRAM_BASE
225# define BL32_LIMIT BL32_DRAM_LIMIT
226#else
227# error "Unsupported RPI3_BL32_RAM_LOCATION_ID value"
228#endif
229#define BL32_SIZE (BL32_LIMIT - BL32_BASE)
230
231#ifdef SPD_none
232#undef BL32_BASE
233#endif /* SPD_none */
234
235/*
236 * Other memory-related defines.
237 */
Antonio Nino Diaz83d8c792018-08-17 14:25:08 +0100238#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
239#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000240
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100241#define MAX_MMAP_REGIONS 8
242#define MAX_XLAT_TABLES 4
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000243
244#define MAX_IO_DEVICES U(3)
245#define MAX_IO_HANDLES U(4)
246
Ying-Chun Liu (PaulLiu)de6f2f42019-01-30 04:20:38 +0800247#define MAX_IO_BLOCK_DEVICES U(1)
248
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000249/*
250 * Serial-related constants.
251 */
252#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
253#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ
254#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
255
256/*
257 * System counter
258 */
259#define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000)
260
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000261#endif /* PLATFORM_DEF_H */