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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
27 ``aarch64``.
28
29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
32 :ref:`Firmware Design`.
33
34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
37
38- ``BL2``: This is an optional build option which specifies the path to BL2
39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
40 built.
41
42- ``BL2U``: This is an optional build option which specifies the path to
43 BL2U image. In this case, the BL2U in TF-A will not be built.
44
45- ``BL2_AT_EL3``: This is an optional build option that enables the use of
46 BL2 at EL3 execution level.
47
48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
50 the RW sections in RAM, while leaving the RO sections in place. This option
51 enable this use-case. For now, this option is only supported when BL2_AT_EL3
52 is set to '1'.
53
54- ``BL31``: This is an optional build option which specifies the path to
55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
56 be built.
57
58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
60 this file name will be used to save the key.
61
62- ``BL32``: This is an optional build option which specifies the path to
63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
64 be built.
65
66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
67 Trusted OS Extra1 image for the ``fip`` target.
68
69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
70 Trusted OS Extra2 image for the ``fip`` target.
71
72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
74 this file name will be used to save the key.
75
76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
77 ``fip`` target in case TF-A BL2 is used.
78
79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
81 this file name will be used to save the key.
82
83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
85 If enabled, it is needed to use a compiler that supports the option
86 ``-mbranch-protection``. Selects the branch protection features to use:
87- 0: Default value turns off all types of branch protection
88- 1: Enables all types of branch protection features
89- 2: Return address signing to its standard level
90- 3: Extend the signing to include leaf functions
91
92 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
93 and resulting PAuth/BTI features.
94
95 +-------+--------------+-------+-----+
96 | Value | GCC option | PAuth | BTI |
97 +=======+==============+=======+=====+
98 | 0 | none | N | N |
99 +-------+--------------+-------+-----+
100 | 1 | standard | Y | Y |
101 +-------+--------------+-------+-----+
102 | 2 | pac-ret | Y | N |
103 +-------+--------------+-------+-----+
104 | 3 | pac-ret+leaf | Y | N |
105 +-------+--------------+-------+-----+
106
107 This option defaults to 0 and this is an experimental feature.
108 Note that Pointer Authentication is enabled for Non-secure world
109 irrespective of the value of this option if the CPU supports it.
110
111- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
112 compilation of each build. It must be set to a C string (including quotes
113 where applicable). Defaults to a string that contains the time and date of
114 the compilation.
115
116- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
117 build to be uniquely identified. Defaults to the current git commit id.
118
119- ``CFLAGS``: Extra user options appended on the compiler's command line in
120 addition to the options set by the build system.
121
122- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
123 release several CPUs out of reset. It can take either 0 (several CPUs may be
124 brought up) or 1 (only one CPU will ever be brought up during cold reset).
125 Default is 0. If the platform always brings up a single CPU, there is no
126 need to distinguish between primary and secondary CPUs and the boot path can
127 be optimised. The ``plat_is_my_cpu_primary()`` and
128 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
129 to be implemented in this case.
130
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100131- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
132 Defaults to ``tbbr``.
133
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100134- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
135 register state when an unexpected exception occurs during execution of
136 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
137 this is only enabled for a debug build of the firmware.
138
139- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
140 certificate generation tool to create new keys in case no valid keys are
141 present or specified. Allowed options are '0' or '1'. Default is '1'.
142
143- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
144 the AArch32 system registers to be included when saving and restoring the
145 CPU context. The option must be set to 0 for AArch64-only platforms (that
146 is on hardware that does not implement AArch32, or at least not at EL1 and
147 higher ELs). Default value is 1.
148
149- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
150 registers to be included when saving and restoring the CPU context. Default
151 is 0.
152
153- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
154 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
155 registers to be included when saving and restoring the CPU context as
156 part of world switch. Default value is 0 and this is an experimental feature.
157 Note that Pointer Authentication is enabled for Non-secure world irrespective
158 of the value of this flag if the CPU supports it.
159
160- ``DEBUG``: Chooses between a debug and release build. It can take either 0
161 (release) or 1 (debug) as values. 0 is the default.
162
Sumit Garg392e4df2019-11-15 10:43:00 +0530163- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
164 authenticated decryption algorithm to be used to decrypt firmware/s during
165 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
166 this flag is ``none`` to disable firmware decryption which is an optional
167 feature as per TBBR. Also, it is an experimental feature.
168
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100169- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
170 of the binary image. If set to 1, then only the ELF image is built.
171 0 is the default.
172
173- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
174 Board Boot authentication at runtime. This option is meant to be enabled only
175 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
176 flag has to be enabled. 0 is the default.
177
178- ``E``: Boolean option to make warnings into errors. Default is 1.
179
180- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
181 the normal boot flow. It must specify the entry point address of the EL3
182 payload. Please refer to the "Booting an EL3 payload" section for more
183 details.
184
185- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
186 This is an optional architectural feature available on v8.4 onwards. Some
187 v8.2 implementations also implement an AMU and this option can be used to
188 enable this feature on those systems as well. Default is 0.
189
190- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
191 are compiled out. For debug builds, this option defaults to 1, and calls to
192 ``assert()`` are left in place. For release builds, this option defaults to 0
193 and calls to ``assert()`` function are compiled out. This option can be set
194 independently of ``DEBUG``. It can also be used to hide any auxiliary code
195 that is only required for the assertion and does not fit in the assertion
196 itself.
197
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000198- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100199 dumps or not. It is supported in both AArch64 and AArch32. However, in
200 AArch32 the format of the frame records are not defined in the AAPCS and they
201 are defined by the implementation. This implementation of backtrace only
202 supports the format used by GCC when T32 interworking is disabled. For this
203 reason enabling this option in AArch32 will force the compiler to only
204 generate A32 code. This option is enabled by default only in AArch64 debug
205 builds, but this behaviour can be overridden in each platform's Makefile or
206 in the build command line.
207
Sandrine Bailleux11427302019-12-17 09:38:08 +0100208- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600209 support in GCC for TF-A. This option is currently only supported for
210 AArch64. Default is 0.
211
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100212- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
213 feature. MPAM is an optional Armv8.4 extension that enables various memory
214 system components and resources to define partitions; software running at
215 various ELs can assign themselves to desired partition to control their
216 performance aspects.
217
218 When this option is set to ``1``, EL3 allows lower ELs to access their own
219 MPAM registers without trapping into EL3. This option doesn't make use of
220 partitioning in EL3, however. Platform initialisation code should configure
221 and use partitions in EL3 as required. This option defaults to ``0``.
222
223- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
224 support within generic code in TF-A. This option is currently only supported
Masahiro Yamadade634f82020-01-17 13:45:14 +0900225 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100226
227- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
228 Measurement Framework(PMF). Default is 0.
229
230- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
231 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
232 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
233 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
234 software.
235
236- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
237 instrumentation which injects timestamp collection points into TF-A to
238 allow runtime performance to be measured. Currently, only PSCI is
239 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
240 as well. Default is 0.
241
242- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
243 extensions. This is an optional architectural feature for AArch64.
244 The default is 1 but is automatically disabled when the target architecture
245 is AArch32.
246
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100247- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
248 (SVE) for the Non-secure world only. SVE is an optional architectural feature
249 for AArch64. Note that when SVE is enabled for the Non-secure world, access
250 to SIMD and floating-point functionality from the Secure world is disabled.
251 This is to avoid corruption of the Non-secure world data in the Z-registers
252 which are aliased by the SIMD and FP registers. The build option is not
253 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
254 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
255 1. The default is 1 but is automatically disabled when the target
256 architecture is AArch32.
257
258- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
259 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
260 default value is set to "none". "strong" is the recommended stack protection
261 level if this feature is desired. "none" disables the stack protection. For
262 all values other than "none", the ``plat_get_stack_protector_canary()``
263 platform hook needs to be implemented. The value is passed as the last
264 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
265
Sumit Gargc0c369c2019-11-15 18:47:53 +0530266- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
267 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as
268 experimental.
269
270- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
271 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as
272 experimental.
273
274- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
275 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
276 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental.
277
278- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
279 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
280 build flag which is marked as experimental.
281
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100282- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
283 deprecated platform APIs, helper functions or drivers within Trusted
284 Firmware as error. It can take the value 1 (flag the use of deprecated
285 APIs as error) or 0. The default is 0.
286
287- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
288 targeted at EL3. When set ``0`` (default), no exceptions are expected or
289 handled at EL3, and a panic will result. This is supported only for AArch64
290 builds.
291
292- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
293 injection from lower ELs, and this build option enables lower ELs to use
294 Error Records accessed via System Registers to inject faults. This is
295 applicable only to AArch64 builds.
296
297 This feature is intended for testing purposes only, and is advisable to keep
298 disabled for production images.
299
300- ``FIP_NAME``: This is an optional build option which specifies the FIP
301 filename for the ``fip`` target. Default is ``fip.bin``.
302
303- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
304 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
305
Sumit Gargc0c369c2019-11-15 18:47:53 +0530306- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
307
308 ::
309
310 0: Encryption is done with Secret Symmetric Key (SSK) which is common
311 for a class of devices.
312 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
313 unique per device.
314
315 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as
316 experimental.
317
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100318- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
319 tool to create certificates as per the Chain of Trust described in
320 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
321 include the certificates in the FIP and FWU_FIP. Default value is '0'.
322
323 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
324 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
325 the corresponding certificates, and to include those certificates in the
326 FIP and FWU_FIP.
327
328 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
329 images will not include support for Trusted Board Boot. The FIP will still
330 include the corresponding certificates. This FIP can be used to verify the
331 Chain of Trust on the host machine through other mechanisms.
332
333 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
334 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
335 will not include the corresponding certificates, causing a boot failure.
336
337- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
338 inherent support for specific EL3 type interrupts. Setting this build option
339 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
340 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
341 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
342 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
343 the Secure Payload interrupts needs to be synchronously handed over to Secure
344 EL1 for handling. The default value of this option is ``0``, which means the
345 Group 0 interrupts are assumed to be handled by Secure EL1.
346
Imre Kisc83f7202020-02-03 14:48:21 +0100347 .. __: platform-interrupt-controller-API.rst
348 .. __: interrupt-framework-design.rst
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100349
350- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
351 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
352 ``0`` (default), these exceptions will be trapped in the current exception
353 level (or in EL1 if the current exception level is EL0).
354
355- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
356 software operations are required for CPUs to enter and exit coherency.
357 However, newer systems exist where CPUs' entry to and exit from coherency
358 is managed in hardware. Such systems require software to only initiate these
359 operations, and the rest is managed in hardware, minimizing active software
360 management. In such systems, this boolean option enables TF-A to carry out
361 build and run-time optimizations during boot and power management operations.
362 This option defaults to 0 and if it is enabled, then it implies
363 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
364
365 If this flag is disabled while the platform which TF-A is compiled for
366 includes cores that manage coherency in hardware, then a compilation error is
367 generated. This is based on the fact that a system cannot have, at the same
368 time, cores that manage coherency in hardware and cores that don't. In other
369 words, a platform cannot have, at the same time, cores that require
370 ``HW_ASSISTED_COHERENCY=1`` and cores that require
371 ``HW_ASSISTED_COHERENCY=0``.
372
373 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
374 translation library (xlat tables v2) must be used; version 1 of translation
375 library is not supported.
376
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000377- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
378 bottom, higher addresses at the top. This buid flag can be set to '1' to
379 invert this behavior. Lower addresses will be printed at the top and higher
380 addresses at the bottom.
381
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100382- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
383 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
384 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
385 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
386 images.
387
388- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
389 used for generating the PKCS keys and subsequent signing of the certificate.
390 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
391 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
392 compliant and is retained only for compatibility. The default value of this
393 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
394
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300395- ``KEY_SIZE``: This build flag enables the user to select the key size for
396 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
397 depend on the chosen algorithm and the cryptographic module.
398
399 +-----------+------------------------------------+
400 | KEY_ALG | Possible key sizes |
401 +===========+====================================+
402 | rsa | 1024 , 2048 (default), 3072, 4096* |
403 +-----------+------------------------------------+
404 | ecdsa | unavailable |
405 +-----------+------------------------------------+
406
407 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
408 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
409
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100410- ``HASH_ALG``: This build flag enables the user to select the secure hash
411 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
412 The default value of this flag is ``sha256``.
413
414- ``LDFLAGS``: Extra user options appended to the linkers' command line in
415 addition to the one set by the build system.
416
417- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
418 output compiled into the build. This should be one of the following:
419
420 ::
421
422 0 (LOG_LEVEL_NONE)
423 10 (LOG_LEVEL_ERROR)
424 20 (LOG_LEVEL_NOTICE)
425 30 (LOG_LEVEL_WARNING)
426 40 (LOG_LEVEL_INFO)
427 50 (LOG_LEVEL_VERBOSE)
428
429 All log output up to and including the selected log level is compiled into
430 the build. The default value is 40 in debug builds and 20 in release builds.
431
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000432- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
433 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set.
434 This option defaults to 0 and is an experimental feature in the stage of
435 development.
436
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100437- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
438 specifies the file that contains the Non-Trusted World private key in PEM
439 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
440
441- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
442 optional. It is only needed if the platform makefile specifies that it
443 is required in order to build the ``fwu_fip`` target.
444
445- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
446 contents upon world switch. It can take either 0 (don't save and restore) or
447 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
448 wants the timer registers to be saved and restored.
449
450- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
451 for the BL image. It can be either 0 (include) or 1 (remove). The default
452 value is 0.
453
454- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
455 the underlying hardware is not a full PL011 UART but a minimally compliant
456 generic UART, which is a subset of the PL011. The driver will not access
457 any register that is not part of the SBSA generic UART specification.
458 Default value is 0 (a full PL011 compliant UART is present).
459
460- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
461 must be subdirectory of any depth under ``plat/``, and must contain a
462 platform makefile named ``platform.mk``. For example, to build TF-A for the
463 Arm Juno board, select PLAT=juno.
464
465- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
466 instead of the normal boot flow. When defined, it must specify the entry
467 point address for the preloaded BL33 image. This option is incompatible with
468 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
469 over ``PRELOADED_BL33_BASE``.
470
471- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
472 vector address can be programmed or is fixed on the platform. It can take
473 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
474 programmable reset address, it is expected that a CPU will start executing
475 code directly at the right address, both on a cold and warm reset. In this
476 case, there is no need to identify the entrypoint on boot and the boot path
477 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
478 does not need to be implemented in this case.
479
480- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
481 possible for the PSCI power-state parameter: original and extended State-ID
482 formats. This flag if set to 1, configures the generic PSCI layer to use the
483 extended format. The default value of this flag is 0, which means by default
484 the original power-state format is used by the PSCI implementation. This flag
485 should be specified by the platform makefile and it governs the return value
486 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
487 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
488 set to 1 as well.
489
490- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
491 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
492 or later CPUs.
493
494 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
495 set to ``1``.
496
497 This option is disabled by default.
498
499- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
500 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
501 entrypoint) or 1 (CPU reset to BL31 entrypoint).
502 The default value is 0.
503
504- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
505 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
506 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
507 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
508
509- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000510 file that contains the ROT private key in PEM format and enforces public key
511 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100512 file name will be used to save the key.
513
514- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
515 certificate generation tool to save the keys used to establish the Chain of
516 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
517
518- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
519 If a SCP_BL2 image is present then this option must be passed for the ``fip``
520 target.
521
522- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
523 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
524 this file name will be used to save the key.
525
526- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
527 optional. It is only needed if the platform makefile specifies that it
528 is required in order to build the ``fwu_fip`` target.
529
530- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
531 Delegated Exception Interface to BL31 image. This defaults to ``0``.
532
533 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
534 set to ``1``.
535
536- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
537 isolated on separate memory pages. This is a trade-off between security and
538 memory usage. See "Isolating code and read-only data on separate memory
539 pages" section in :ref:`Firmware Design`. This flag is disabled by default and
540 affects all BL images.
541
Samuel Holland31a14e12018-10-17 21:40:18 -0500542- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
543 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
544 allocated in RAM discontiguous from the loaded firmware image. When set, the
545 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
546 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
547 sections are placed in RAM immediately following the loaded firmware image.
548
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100549- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
550 This build option is only valid if ``ARCH=aarch64``. The value should be
551 the path to the directory containing the SPD source, relative to
552 ``services/spd/``; the directory is expected to contain a makefile called
553 ``<spd-value>.mk``.
554
555- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
556 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
557 execution in BL1 just before handing over to BL31. At this point, all
558 firmware images have been loaded in memory, and the MMU and caches are
559 turned off. Refer to the "Debugging options" section for more details.
560
Paul Beesleyfe975b42019-09-16 11:29:03 +0000561- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
562 Partition Manager (SPM) implementation. The default value is ``0``.
563
Manish Pandey3f90ad72020-01-14 11:52:05 +0000564- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
565 description of secure partitions. Build system will parse this file and
566 package all secure partition blobs in FIP. This file not necessarily be
567 part of TF-A tree. Only avaialbe when ``SPD=spmd``.
568
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100569- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
570 secure interrupts (caught through the FIQ line). Platforms can enable
571 this directive if they need to handle such interruption. When enabled,
572 the FIQ are handled in monitor mode and non secure world is not allowed
573 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
574 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
575
576- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
577 Boot feature. When set to '1', BL1 and BL2 images include support to load
578 and verify the certificates and images in a FIP, and BL1 includes support
579 for the Firmware Update. The default value is '0'. Generation and inclusion
580 of certificates in the FIP and FWU_FIP depends upon the value of the
581 ``GENERATE_COT`` option.
582
583 .. warning::
584 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
585 already exist in disk, they will be overwritten without further notice.
586
587- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
588 specifies the file that contains the Trusted World private key in PEM
589 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
590
591- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
592 synchronous, (see "Initializing a BL32 Image" section in
593 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
594 synchronous method) or 1 (BL32 is initialized using asynchronous method).
595 Default is 0.
596
597- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
598 routing model which routes non-secure interrupts asynchronously from TSP
599 to EL3 causing immediate preemption of TSP. The EL3 is responsible
600 for saving and restoring the TSP context in this routing model. The
601 default routing model (when the value is 0) is to route non-secure
602 interrupts to TSP allowing it to save its context and hand over
603 synchronously to EL3 via an SMC.
604
605 .. note::
606 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
607 must also be set to ``1``.
608
609- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
610 linker. When the ``LINKER`` build variable points to the armlink linker,
611 this flag is enabled automatically. To enable support for armlink, platforms
612 will have to provide a scatter file for the BL image. Currently, Tegra
613 platforms use the armlink support to compile BL3-1 images.
614
615- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
616 memory region in the BL memory map or not (see "Use of Coherent memory in
617 TF-A" section in :ref:`Firmware Design`). It can take the value 1
618 (Coherent memory region is included) or 0 (Coherent memory region is
619 excluded). Default is 1.
620
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100621- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
622 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
623 Default is 0.
624
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100625- ``USE_FCONF_BASED_IO``: This flag determines whether to use IO based on the
626 firmware configuration framework. This allows moving the io_policies into a
627 configuration device tree, instead of static structure in the code base.
628
629
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100630- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
631 This feature creates a library of functions to be placed in ROM and thus
632 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
633 is 0.
634
635- ``V``: Verbose build. If assigned anything other than 0, the build commands
636 are printed. Default is 0.
637
638- ``VERSION_STRING``: String used in the log output for each TF-A image.
639 Defaults to a string formed by concatenating the version number, build type
640 and build string.
641
642- ``W``: Warning level. Some compiler warning options of interest have been
643 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
644 each level enabling more warning options. Default is 0.
645
646- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
647 the CPU after warm boot. This is applicable for platforms which do not
648 require interconnect programming to enable cache coherency (eg: single
649 cluster platforms). If this option is enabled, then warm boot path
650 enables D-caches immediately after enabling MMU. This option defaults to 0.
651
652Debugging options
653-----------------
654
655To compile a debug version and make the build more verbose use
656
657.. code:: shell
658
659 make PLAT=<platform> DEBUG=1 V=1 all
660
661AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
662example DS-5) might not support this and may need an older version of DWARF
663symbols to be emitted by GCC. This can be achieved by using the
664``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
665version to 2 is recommended for DS-5 versions older than 5.16.
666
667When debugging logic problems it might also be useful to disable all compiler
668optimizations by using ``-O0``.
669
670.. warning::
671 Using ``-O0`` could cause output images to be larger and base addresses
672 might need to be recalculated (see the **Memory layout on Arm development
673 platforms** section in the :ref:`Firmware Design`).
674
675Extra debug options can be passed to the build system by setting ``CFLAGS`` or
676``LDFLAGS``:
677
678.. code:: shell
679
680 CFLAGS='-O0 -gdwarf-2' \
681 make PLAT=<platform> DEBUG=1 V=1 all
682
683Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
684ignored as the linker is called directly.
685
686It is also possible to introduce an infinite loop to help in debugging the
687post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
688``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
689section. In this case, the developer may take control of the target using a
690debugger when indicated by the console output. When using DS-5, the following
691commands can be used:
692
693::
694
695 # Stop target execution
696 interrupt
697
698 #
699 # Prepare your debugging environment, e.g. set breakpoints
700 #
701
702 # Jump over the debug loop
703 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
704
705 # Resume execution
706 continue
707
708--------------
709
Imre Kisc83f7202020-02-03 14:48:21 +0100710*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*