Sheetal Tigadoli | b015670 | 2020-01-05 14:59:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 - 2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef BRCM_RDB_SD4_EMMC_TOP_H |
| 8 | #define BRCM_RDB_SD4_EMMC_TOP_H |
| 9 | |
| 10 | #define SD4_EMMC_TOP_SYSADDR_OFFSET 0x00000000 |
| 11 | #define SD4_EMMC_TOP_SYSADDR_DEFAULT 0x00000000 |
| 12 | #define SD4_EMMC_TOP_SYSADDR_TYPE uint32_t |
| 13 | #define SD4_EMMC_TOP_SYSADDR_RESERVED_MASK 0x00000000 |
| 14 | #define SD4_EMMC_TOP_SYSADDR_SYSADDR_SHIFT 0 |
| 15 | #define SD4_EMMC_TOP_SYSADDR_SYSADDR_MASK 0xFFFFFFFF |
| 16 | |
| 17 | #define SD4_EMMC_TOP_BLOCK_OFFSET 0x00000004 |
| 18 | #define SD4_EMMC_TOP_BLOCK_DEFAULT 0x00000000 |
| 19 | #define SD4_EMMC_TOP_BLOCK_TYPE uint32_t |
| 20 | #define SD4_EMMC_TOP_BLOCK_RESERVED_MASK 0x00008000 |
| 21 | #define SD4_EMMC_TOP_BLOCK_BCNT_SHIFT 16 |
| 22 | #define SD4_EMMC_TOP_BLOCK_BCNT_MASK 0xFFFF0000 |
| 23 | #define SD4_EMMC_TOP_BLOCK_HSBS_SHIFT 12 |
| 24 | #define SD4_EMMC_TOP_BLOCK_HSBS_MASK 0x00007000 |
| 25 | #define SD4_EMMC_TOP_BLOCK_TBS_SHIFT 0 |
| 26 | #define SD4_EMMC_TOP_BLOCK_TBS_MASK 0x00000FFF |
| 27 | |
| 28 | #define SD4_EMMC_TOP_ARG_OFFSET 0x00000008 |
| 29 | #define SD4_EMMC_TOP_ARG_DEFAULT 0x00000000 |
| 30 | #define SD4_EMMC_TOP_ARG_TYPE uint32_t |
| 31 | #define SD4_EMMC_TOP_ARG_RESERVED_MASK 0x00000000 |
| 32 | #define SD4_EMMC_TOP_ARG_ARG_SHIFT 0 |
| 33 | #define SD4_EMMC_TOP_ARG_ARG_MASK 0xFFFFFFFF |
| 34 | |
| 35 | #define SD4_EMMC_TOP_CMD_OFFSET 0x0000000C |
| 36 | #define SD4_EMMC_TOP_CMD_DEFAULT 0x00000000 |
| 37 | #define SD4_EMMC_TOP_CMD_TYPE uint32_t |
| 38 | #define SD4_EMMC_TOP_CMD_RESERVED_MASK 0xC004FFC0 |
| 39 | #define SD4_EMMC_TOP_CMD_CIDX_SHIFT 24 |
| 40 | #define SD4_EMMC_TOP_CMD_CIDX_MASK 0x3F000000 |
| 41 | #define SD4_EMMC_TOP_CMD_CTYP_SHIFT 22 |
| 42 | #define SD4_EMMC_TOP_CMD_CTYP_MASK 0x00C00000 |
| 43 | #define SD4_EMMC_TOP_CMD_DPS_SHIFT 21 |
| 44 | #define SD4_EMMC_TOP_CMD_DPS_MASK 0x00200000 |
| 45 | #define SD4_EMMC_TOP_CMD_CCHK_EN_SHIFT 20 |
| 46 | #define SD4_EMMC_TOP_CMD_CCHK_EN_MASK 0x00100000 |
| 47 | #define SD4_EMMC_TOP_CMD_CRC_EN_SHIFT 19 |
| 48 | #define SD4_EMMC_TOP_CMD_CRC_EN_MASK 0x00080000 |
| 49 | #define SD4_EMMC_TOP_CMD_RTSEL_SHIFT 16 |
| 50 | #define SD4_EMMC_TOP_CMD_RTSEL_MASK 0x00030000 |
| 51 | #define SD4_EMMC_TOP_CMD_MSBS_SHIFT 5 |
| 52 | #define SD4_EMMC_TOP_CMD_MSBS_MASK 0x00000020 |
| 53 | #define SD4_EMMC_TOP_CMD_DTDS_SHIFT 4 |
| 54 | #define SD4_EMMC_TOP_CMD_DTDS_MASK 0x00000010 |
| 55 | #define SD4_EMMC_TOP_CMD_ACMDEN_SHIFT 2 |
| 56 | #define SD4_EMMC_TOP_CMD_ACMDEN_MASK 0x0000000C |
| 57 | #define SD4_EMMC_TOP_CMD_BCEN_SHIFT 1 |
| 58 | #define SD4_EMMC_TOP_CMD_BCEN_MASK 0x00000002 |
| 59 | #define SD4_EMMC_TOP_CMD_DMA_SHIFT 0 |
| 60 | #define SD4_EMMC_TOP_CMD_DMA_MASK 0x00000001 |
| 61 | |
| 62 | #define SD4_EMMC_TOP_CMD_SD4_OFFSET 0x0000000C |
| 63 | #define SD4_EMMC_TOP_CMD_SD4_DEFAULT 0x00000000 |
| 64 | #define SD4_EMMC_TOP_CMD_SD4_TYPE uint32_t |
| 65 | #define SD4_EMMC_TOP_CMD_SD4_RESERVED_MASK 0xC004FE00 |
| 66 | #define SD4_EMMC_TOP_CMD_SD4_CIDX_SHIFT 24 |
| 67 | #define SD4_EMMC_TOP_CMD_SD4_CIDX_MASK 0x3F000000 |
| 68 | #define SD4_EMMC_TOP_CMD_SD4_CTYP_SHIFT 22 |
| 69 | #define SD4_EMMC_TOP_CMD_SD4_CTYP_MASK 0x00C00000 |
| 70 | #define SD4_EMMC_TOP_CMD_SD4_DPS_SHIFT 21 |
| 71 | #define SD4_EMMC_TOP_CMD_SD4_DPS_MASK 0x00200000 |
| 72 | #define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_SHIFT 20 |
| 73 | #define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_MASK 0x00100000 |
| 74 | #define SD4_EMMC_TOP_CMD_SD4_CRC_EN_SHIFT 19 |
| 75 | #define SD4_EMMC_TOP_CMD_SD4_CRC_EN_MASK 0x00080000 |
| 76 | #define SD4_EMMC_TOP_CMD_SD4_RTSEL_SHIFT 16 |
| 77 | #define SD4_EMMC_TOP_CMD_SD4_RTSEL_MASK 0x00030000 |
| 78 | #define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_SHIFT 8 |
| 79 | #define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_MASK 0x00000100 |
| 80 | #define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_SHIFT 7 |
| 81 | #define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_MASK 0x00000080 |
| 82 | #define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_SHIFT 6 |
| 83 | #define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_MASK 0x00000040 |
| 84 | #define SD4_EMMC_TOP_CMD_SD4_MSBS_SHIFT 5 |
| 85 | #define SD4_EMMC_TOP_CMD_SD4_MSBS_MASK 0x00000020 |
| 86 | #define SD4_EMMC_TOP_CMD_SD4_DTDS_SHIFT 4 |
| 87 | #define SD4_EMMC_TOP_CMD_SD4_DTDS_MASK 0x00000010 |
| 88 | #define SD4_EMMC_TOP_CMD_SD4_ACMDEN_SHIFT 2 |
| 89 | #define SD4_EMMC_TOP_CMD_SD4_ACMDEN_MASK 0x0000000C |
| 90 | #define SD4_EMMC_TOP_CMD_SD4_BCEN_SHIFT 1 |
| 91 | #define SD4_EMMC_TOP_CMD_SD4_BCEN_MASK 0x00000002 |
| 92 | #define SD4_EMMC_TOP_CMD_SD4_DMA_SHIFT 0 |
| 93 | #define SD4_EMMC_TOP_CMD_SD4_DMA_MASK 0x00000001 |
| 94 | |
| 95 | #define SD4_EMMC_TOP_RESP0_OFFSET 0x00000010 |
| 96 | #define SD4_EMMC_TOP_RESP0_DEFAULT 0x00000000 |
| 97 | #define SD4_EMMC_TOP_RESP0_TYPE uint32_t |
| 98 | #define SD4_EMMC_TOP_RESP0_RESERVED_MASK 0x00000000 |
| 99 | #define SD4_EMMC_TOP_RESP0_RESP0_SHIFT 0 |
| 100 | #define SD4_EMMC_TOP_RESP0_RESP0_MASK 0xFFFFFFFF |
| 101 | |
| 102 | #define SD4_EMMC_TOP_RESP2_OFFSET 0x00000014 |
| 103 | #define SD4_EMMC_TOP_RESP2_DEFAULT 0x00000000 |
| 104 | #define SD4_EMMC_TOP_RESP2_TYPE uint32_t |
| 105 | #define SD4_EMMC_TOP_RESP2_RESERVED_MASK 0x00000000 |
| 106 | #define SD4_EMMC_TOP_RESP2_RESP2_SHIFT 0 |
| 107 | #define SD4_EMMC_TOP_RESP2_RESP2_MASK 0xFFFFFFFF |
| 108 | |
| 109 | #define SD4_EMMC_TOP_RESP4_OFFSET 0x00000018 |
| 110 | #define SD4_EMMC_TOP_RESP4_DEFAULT 0x00000000 |
| 111 | #define SD4_EMMC_TOP_RESP4_TYPE uint32_t |
| 112 | #define SD4_EMMC_TOP_RESP4_RESERVED_MASK 0x00000000 |
| 113 | #define SD4_EMMC_TOP_RESP4_RESP4_SHIFT 0 |
| 114 | #define SD4_EMMC_TOP_RESP4_RESP4_MASK 0xFFFFFFFF |
| 115 | |
| 116 | #define SD4_EMMC_TOP_RESP6_OFFSET 0x0000001C |
| 117 | #define SD4_EMMC_TOP_RESP6_DEFAULT 0x00000000 |
| 118 | #define SD4_EMMC_TOP_RESP6_TYPE uint32_t |
| 119 | #define SD4_EMMC_TOP_RESP6_RESERVED_MASK 0x00000000 |
| 120 | #define SD4_EMMC_TOP_RESP6_RESP6_SHIFT 0 |
| 121 | #define SD4_EMMC_TOP_RESP6_RESP6_MASK 0xFFFFFFFF |
| 122 | |
| 123 | #define SD4_EMMC_TOP_BUFDAT_OFFSET 0x00000020 |
| 124 | #define SD4_EMMC_TOP_BUFDAT_DEFAULT 0x00000000 |
| 125 | #define SD4_EMMC_TOP_BUFDAT_TYPE uint32_t |
| 126 | #define SD4_EMMC_TOP_BUFDAT_RESERVED_MASK 0x00000000 |
| 127 | #define SD4_EMMC_TOP_BUFDAT_BUFDAT_SHIFT 0 |
| 128 | #define SD4_EMMC_TOP_BUFDAT_BUFDAT_MASK 0xFFFFFFFF |
| 129 | |
| 130 | #define SD4_EMMC_TOP_PSTATE_OFFSET 0x00000024 |
| 131 | #define SD4_EMMC_TOP_PSTATE_DEFAULT 0x1FFC0000 |
| 132 | #define SD4_EMMC_TOP_PSTATE_TYPE uint32_t |
| 133 | #define SD4_EMMC_TOP_PSTATE_RESERVED_MASK 0xE000F0F0 |
| 134 | #define SD4_EMMC_TOP_PSTATE_DLS7_4_SHIFT 25 |
| 135 | #define SD4_EMMC_TOP_PSTATE_DLS7_4_MASK 0x1E000000 |
| 136 | #define SD4_EMMC_TOP_PSTATE_CLSL_SHIFT 24 |
| 137 | #define SD4_EMMC_TOP_PSTATE_CLSL_MASK 0x01000000 |
| 138 | #define SD4_EMMC_TOP_PSTATE_DLS3_0_SHIFT 20 |
| 139 | #define SD4_EMMC_TOP_PSTATE_DLS3_0_MASK 0x00F00000 |
| 140 | #define SD4_EMMC_TOP_PSTATE_WPSL_SHIFT 19 |
| 141 | #define SD4_EMMC_TOP_PSTATE_WPSL_MASK 0x00080000 |
| 142 | #define SD4_EMMC_TOP_PSTATE_CDPL_SHIFT 18 |
| 143 | #define SD4_EMMC_TOP_PSTATE_CDPL_MASK 0x00040000 |
| 144 | #define SD4_EMMC_TOP_PSTATE_CSS_SHIFT 17 |
| 145 | #define SD4_EMMC_TOP_PSTATE_CSS_MASK 0x00020000 |
| 146 | #define SD4_EMMC_TOP_PSTATE_CINS_SHIFT 16 |
| 147 | #define SD4_EMMC_TOP_PSTATE_CINS_MASK 0x00010000 |
| 148 | #define SD4_EMMC_TOP_PSTATE_BREN_SHIFT 11 |
| 149 | #define SD4_EMMC_TOP_PSTATE_BREN_MASK 0x00000800 |
| 150 | #define SD4_EMMC_TOP_PSTATE_BWEN_SHIFT 10 |
| 151 | #define SD4_EMMC_TOP_PSTATE_BWEN_MASK 0x00000400 |
| 152 | #define SD4_EMMC_TOP_PSTATE_RXACT_SHIFT 9 |
| 153 | #define SD4_EMMC_TOP_PSTATE_RXACT_MASK 0x00000200 |
| 154 | #define SD4_EMMC_TOP_PSTATE_WXACT_SHIFT 8 |
| 155 | #define SD4_EMMC_TOP_PSTATE_WXACT_MASK 0x00000100 |
| 156 | #define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_SHIFT 3 |
| 157 | #define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_MASK 0x00000008 |
| 158 | #define SD4_EMMC_TOP_PSTATE_DATACT_SHIFT 2 |
| 159 | #define SD4_EMMC_TOP_PSTATE_DATACT_MASK 0x00000004 |
| 160 | #define SD4_EMMC_TOP_PSTATE_DATINH_SHIFT 1 |
| 161 | #define SD4_EMMC_TOP_PSTATE_DATINH_MASK 0x00000002 |
| 162 | #define SD4_EMMC_TOP_PSTATE_CMDINH_SHIFT 0 |
| 163 | #define SD4_EMMC_TOP_PSTATE_CMDINH_MASK 0x00000001 |
| 164 | |
| 165 | #define SD4_EMMC_TOP_PSTATE_SD4_OFFSET 0x00000024 |
| 166 | #define SD4_EMMC_TOP_PSTATE_SD4_DEFAULT 0x01FC00F0 |
| 167 | #define SD4_EMMC_TOP_PSTATE_SD4_TYPE uint32_t |
| 168 | #define SD4_EMMC_TOP_PSTATE_SD4_RESERVED_MASK 0x1E00F000 |
| 169 | #define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_SHIFT 31 |
| 170 | #define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_MASK 0x80000000 |
| 171 | #define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_SHIFT 30 |
| 172 | #define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_MASK 0x40000000 |
| 173 | #define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_SHIFT 29 |
| 174 | #define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_MASK 0x20000000 |
| 175 | #define SD4_EMMC_TOP_PSTATE_SD4_CLSL_SHIFT 24 |
| 176 | #define SD4_EMMC_TOP_PSTATE_SD4_CLSL_MASK 0x01000000 |
| 177 | #define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_SHIFT 20 |
| 178 | #define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_MASK 0x00F00000 |
| 179 | #define SD4_EMMC_TOP_PSTATE_SD4_WPSL_SHIFT 19 |
| 180 | #define SD4_EMMC_TOP_PSTATE_SD4_WPSL_MASK 0x00080000 |
| 181 | #define SD4_EMMC_TOP_PSTATE_SD4_CDPL_SHIFT 18 |
| 182 | #define SD4_EMMC_TOP_PSTATE_SD4_CDPL_MASK 0x00040000 |
| 183 | #define SD4_EMMC_TOP_PSTATE_SD4_CSS_SHIFT 17 |
| 184 | #define SD4_EMMC_TOP_PSTATE_SD4_CSS_MASK 0x00020000 |
| 185 | #define SD4_EMMC_TOP_PSTATE_SD4_CINS_SHIFT 16 |
| 186 | #define SD4_EMMC_TOP_PSTATE_SD4_CINS_MASK 0x00010000 |
| 187 | #define SD4_EMMC_TOP_PSTATE_SD4_BREN_SHIFT 11 |
| 188 | #define SD4_EMMC_TOP_PSTATE_SD4_BREN_MASK 0x00000800 |
| 189 | #define SD4_EMMC_TOP_PSTATE_SD4_BWEN_SHIFT 10 |
| 190 | #define SD4_EMMC_TOP_PSTATE_SD4_BWEN_MASK 0x00000400 |
| 191 | #define SD4_EMMC_TOP_PSTATE_SD4_RXACT_SHIFT 9 |
| 192 | #define SD4_EMMC_TOP_PSTATE_SD4_RXACT_MASK 0x00000200 |
| 193 | #define SD4_EMMC_TOP_PSTATE_SD4_WXACT_SHIFT 8 |
| 194 | #define SD4_EMMC_TOP_PSTATE_SD4_WXACT_MASK 0x00000100 |
| 195 | #define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_SHIFT 4 |
| 196 | #define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_MASK 0x000000F0 |
| 197 | #define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_SHIFT 3 |
| 198 | #define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_MASK 0x00000008 |
| 199 | #define SD4_EMMC_TOP_PSTATE_SD4_DATACT_SHIFT 2 |
| 200 | #define SD4_EMMC_TOP_PSTATE_SD4_DATACT_MASK 0x00000004 |
| 201 | #define SD4_EMMC_TOP_PSTATE_SD4_DATINH_SHIFT 1 |
| 202 | #define SD4_EMMC_TOP_PSTATE_SD4_DATINH_MASK 0x00000002 |
| 203 | #define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_SHIFT 0 |
| 204 | #define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_MASK 0x00000001 |
| 205 | |
| 206 | #define SD4_EMMC_TOP_CTRL_OFFSET 0x00000028 |
| 207 | #define SD4_EMMC_TOP_CTRL_DEFAULT 0x00000000 |
| 208 | #define SD4_EMMC_TOP_CTRL_TYPE uint32_t |
| 209 | #define SD4_EMMC_TOP_CTRL_RESERVED_MASK 0xF800E000 |
| 210 | #define SD4_EMMC_TOP_CTRL_WAKENRMV_SHIFT 26 |
| 211 | #define SD4_EMMC_TOP_CTRL_WAKENRMV_MASK 0x04000000 |
| 212 | #define SD4_EMMC_TOP_CTRL_WAKENINS_SHIFT 25 |
| 213 | #define SD4_EMMC_TOP_CTRL_WAKENINS_MASK 0x02000000 |
| 214 | #define SD4_EMMC_TOP_CTRL_WAKENIRQ_SHIFT 24 |
| 215 | #define SD4_EMMC_TOP_CTRL_WAKENIRQ_MASK 0x01000000 |
| 216 | #define SD4_EMMC_TOP_CTRL_BOOTACK_SHIFT 23 |
| 217 | #define SD4_EMMC_TOP_CTRL_BOOTACK_MASK 0x00800000 |
| 218 | #define SD4_EMMC_TOP_CTRL_ATLBOOTEN_SHIFT 22 |
| 219 | #define SD4_EMMC_TOP_CTRL_ATLBOOTEN_MASK 0x00400000 |
| 220 | #define SD4_EMMC_TOP_CTRL_BOOTEN_SHIFT 21 |
| 221 | #define SD4_EMMC_TOP_CTRL_BOOTEN_MASK 0x00200000 |
| 222 | #define SD4_EMMC_TOP_CTRL_SPIMODE_SHIFT 20 |
| 223 | #define SD4_EMMC_TOP_CTRL_SPIMODE_MASK 0x00100000 |
| 224 | #define SD4_EMMC_TOP_CTRL_BLKIRQ_SHIFT 19 |
| 225 | #define SD4_EMMC_TOP_CTRL_BLKIRQ_MASK 0x00080000 |
| 226 | #define SD4_EMMC_TOP_CTRL_RDWTCRTL_SHIFT 18 |
| 227 | #define SD4_EMMC_TOP_CTRL_RDWTCRTL_MASK 0x00040000 |
| 228 | #define SD4_EMMC_TOP_CTRL_CONTREQ_SHIFT 17 |
| 229 | #define SD4_EMMC_TOP_CTRL_CONTREQ_MASK 0x00020000 |
| 230 | #define SD4_EMMC_TOP_CTRL_BLKSTPREQ_SHIFT 16 |
| 231 | #define SD4_EMMC_TOP_CTRL_BLKSTPREQ_MASK 0x00010000 |
| 232 | #define SD4_EMMC_TOP_CTRL_HRESET_SHIFT 12 |
| 233 | #define SD4_EMMC_TOP_CTRL_HRESET_MASK 0x00001000 |
| 234 | #define SD4_EMMC_TOP_CTRL_SDVSELVDD1_SHIFT 9 |
| 235 | #define SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK 0x00000E00 |
| 236 | #define SD4_EMMC_TOP_CTRL_SDPWR_SHIFT 8 |
| 237 | #define SD4_EMMC_TOP_CTRL_SDPWR_MASK 0x00000100 |
| 238 | #define SD4_EMMC_TOP_CTRL_CDSD_SHIFT 7 |
| 239 | #define SD4_EMMC_TOP_CTRL_CDSD_MASK 0x00000080 |
| 240 | #define SD4_EMMC_TOP_CTRL_CDTL_SHIFT 6 |
| 241 | #define SD4_EMMC_TOP_CTRL_CDTL_MASK 0x00000040 |
| 242 | #define SD4_EMMC_TOP_CTRL_SDB_SHIFT 5 |
| 243 | #define SD4_EMMC_TOP_CTRL_SDB_MASK 0x00000020 |
| 244 | #define SD4_EMMC_TOP_CTRL_DMASEL_SHIFT 3 |
| 245 | #define SD4_EMMC_TOP_CTRL_DMASEL_MASK 0x00000018 |
| 246 | #define SD4_EMMC_TOP_CTRL_HSEN_SHIFT 2 |
| 247 | #define SD4_EMMC_TOP_CTRL_HSEN_MASK 0x00000004 |
| 248 | #define SD4_EMMC_TOP_CTRL_DXTW_SHIFT 1 |
| 249 | #define SD4_EMMC_TOP_CTRL_DXTW_MASK 0x00000002 |
| 250 | #define SD4_EMMC_TOP_CTRL_LEDCTL_SHIFT 0 |
| 251 | #define SD4_EMMC_TOP_CTRL_LEDCTL_MASK 0x00000001 |
| 252 | |
| 253 | #define SD4_EMMC_TOP_CTRL_SD4_OFFSET 0x00000028 |
| 254 | #define SD4_EMMC_TOP_CTRL_SD4_DEFAULT 0x00000000 |
| 255 | #define SD4_EMMC_TOP_CTRL_SD4_TYPE uint32_t |
| 256 | #define SD4_EMMC_TOP_CTRL_SD4_RESERVED_MASK 0xF8F00000 |
| 257 | #define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_SHIFT 26 |
| 258 | #define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_MASK 0x04000000 |
| 259 | #define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_SHIFT 25 |
| 260 | #define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_MASK 0x02000000 |
| 261 | #define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_SHIFT 24 |
| 262 | #define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_MASK 0x01000000 |
| 263 | #define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_SHIFT 19 |
| 264 | #define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_MASK 0x00080000 |
| 265 | #define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_SHIFT 18 |
| 266 | #define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_MASK 0x00040000 |
| 267 | #define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_SHIFT 17 |
| 268 | #define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_MASK 0x00020000 |
| 269 | #define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_SHIFT 16 |
| 270 | #define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_MASK 0x00010000 |
| 271 | #define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_SHIFT 13 |
| 272 | #define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_MASK 0x0000E000 |
| 273 | #define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_SHIFT 12 |
| 274 | #define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_MASK 0x00001000 |
| 275 | #define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_SHIFT 9 |
| 276 | #define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_MASK 0x00000E00 |
| 277 | #define SD4_EMMC_TOP_CTRL_SD4_SDPWR_SHIFT 8 |
| 278 | #define SD4_EMMC_TOP_CTRL_SD4_SDPWR_MASK 0x00000100 |
| 279 | #define SD4_EMMC_TOP_CTRL_SD4_CDSD_SHIFT 7 |
| 280 | #define SD4_EMMC_TOP_CTRL_SD4_CDSD_MASK 0x00000080 |
| 281 | #define SD4_EMMC_TOP_CTRL_SD4_CDTL_SHIFT 6 |
| 282 | #define SD4_EMMC_TOP_CTRL_SD4_CDTL_MASK 0x00000040 |
| 283 | #define SD4_EMMC_TOP_CTRL_SD4_SDB_SHIFT 5 |
| 284 | #define SD4_EMMC_TOP_CTRL_SD4_SDB_MASK 0x00000020 |
| 285 | #define SD4_EMMC_TOP_CTRL_SD4_DMASEL_SHIFT 3 |
| 286 | #define SD4_EMMC_TOP_CTRL_SD4_DMASEL_MASK 0x00000018 |
| 287 | #define SD4_EMMC_TOP_CTRL_SD4_HSEN_SHIFT 2 |
| 288 | #define SD4_EMMC_TOP_CTRL_SD4_HSEN_MASK 0x00000004 |
| 289 | #define SD4_EMMC_TOP_CTRL_SD4_DXTW_SHIFT 1 |
| 290 | #define SD4_EMMC_TOP_CTRL_SD4_DXTW_MASK 0x00000002 |
| 291 | #define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_SHIFT 0 |
| 292 | #define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_MASK 0x00000001 |
| 293 | |
| 294 | #define SD4_EMMC_TOP_CTRL1_OFFSET 0x0000002C |
| 295 | #define SD4_EMMC_TOP_CTRL1_DEFAULT 0x00000000 |
| 296 | #define SD4_EMMC_TOP_CTRL1_TYPE uint32_t |
| 297 | #define SD4_EMMC_TOP_CTRL1_RESERVED_MASK 0xF8F00018 |
| 298 | #define SD4_EMMC_TOP_CTRL1_DATRST_SHIFT 26 |
| 299 | #define SD4_EMMC_TOP_CTRL1_DATRST_MASK 0x04000000 |
| 300 | #define SD4_EMMC_TOP_CTRL1_CMDRST_SHIFT 25 |
| 301 | #define SD4_EMMC_TOP_CTRL1_CMDRST_MASK 0x02000000 |
| 302 | #define SD4_EMMC_TOP_CTRL1_RST_SHIFT 24 |
| 303 | #define SD4_EMMC_TOP_CTRL1_RST_MASK 0x01000000 |
| 304 | #define SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT 16 |
| 305 | #define SD4_EMMC_TOP_CTRL1_DTCNT_MASK 0x000F0000 |
| 306 | #define SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT 8 |
| 307 | #define SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK 0x0000FF00 |
| 308 | #define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT 6 |
| 309 | #define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK 0x000000C0 |
| 310 | #define SD4_EMMC_TOP_CTRL1_CLKGENSEL_SHIFT 5 |
| 311 | #define SD4_EMMC_TOP_CTRL1_CLKGENSEL_MASK 0x00000020 |
| 312 | #define SD4_EMMC_TOP_CTRL1_SDCLKEN_SHIFT 2 |
| 313 | #define SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK 0x00000004 |
| 314 | #define SD4_EMMC_TOP_CTRL1_ICLKSTB_SHIFT 1 |
| 315 | #define SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK 0x00000002 |
| 316 | #define SD4_EMMC_TOP_CTRL1_ICLKEN_SHIFT 0 |
| 317 | #define SD4_EMMC_TOP_CTRL1_ICLKEN_MASK 0x00000001 |
| 318 | |
| 319 | #define SD4_EMMC_TOP_INTR_OFFSET 0x00000030 |
| 320 | #define SD4_EMMC_TOP_INTR_DEFAULT 0x00000000 |
| 321 | #define SD4_EMMC_TOP_INTR_TYPE uint32_t |
| 322 | #define SD4_EMMC_TOP_INTR_RESERVED_MASK 0xEC000000 |
| 323 | #define SD4_EMMC_TOP_INTR_TRESPERR_SHIFT 28 |
| 324 | #define SD4_EMMC_TOP_INTR_TRESPERR_MASK 0x10000000 |
| 325 | #define SD4_EMMC_TOP_INTR_ADMAERR_SHIFT 25 |
| 326 | #define SD4_EMMC_TOP_INTR_ADMAERR_MASK 0x02000000 |
| 327 | #define SD4_EMMC_TOP_INTR_CMDERROR_SHIFT 24 |
| 328 | #define SD4_EMMC_TOP_INTR_CMDERROR_MASK 0x01000000 |
| 329 | #define SD4_EMMC_TOP_INTR_IERR_SHIFT 23 |
| 330 | #define SD4_EMMC_TOP_INTR_IERR_MASK 0x00800000 |
| 331 | #define SD4_EMMC_TOP_INTR_DEBERR_SHIFT 22 |
| 332 | #define SD4_EMMC_TOP_INTR_DEBERR_MASK 0x00400000 |
| 333 | #define SD4_EMMC_TOP_INTR_DCRCERR_SHIFT 21 |
| 334 | #define SD4_EMMC_TOP_INTR_DCRCERR_MASK 0x00200000 |
| 335 | #define SD4_EMMC_TOP_INTR_DTOERR_SHIFT 20 |
| 336 | #define SD4_EMMC_TOP_INTR_DTOERR_MASK 0x00100000 |
| 337 | #define SD4_EMMC_TOP_INTR_CMDIDXERR_SHIFT 19 |
| 338 | #define SD4_EMMC_TOP_INTR_CMDIDXERR_MASK 0x00080000 |
| 339 | #define SD4_EMMC_TOP_INTR_CEBERR_SHIFT 18 |
| 340 | #define SD4_EMMC_TOP_INTR_CEBERR_MASK 0x00040000 |
| 341 | #define SD4_EMMC_TOP_INTR_CCRCERR_SHIFT 17 |
| 342 | #define SD4_EMMC_TOP_INTR_CCRCERR_MASK 0x00020000 |
| 343 | #define SD4_EMMC_TOP_INTR_CTOERR_SHIFT 16 |
| 344 | #define SD4_EMMC_TOP_INTR_CTOERR_MASK 0x00010000 |
| 345 | #define SD4_EMMC_TOP_INTR_ERRIRQ_SHIFT 15 |
| 346 | #define SD4_EMMC_TOP_INTR_ERRIRQ_MASK 0x00008000 |
| 347 | #define SD4_EMMC_TOP_INTR_BTIRQ_SHIFT 14 |
| 348 | #define SD4_EMMC_TOP_INTR_BTIRQ_MASK 0x00004000 |
| 349 | #define SD4_EMMC_TOP_INTR_BTACKRX_SHIFT 13 |
| 350 | #define SD4_EMMC_TOP_INTR_BTACKRX_MASK 0x00002000 |
| 351 | #define SD4_EMMC_TOP_INTR_RETUNE_EVENT_SHIFT 12 |
| 352 | #define SD4_EMMC_TOP_INTR_RETUNE_EVENT_MASK 0x00001000 |
| 353 | #define SD4_EMMC_TOP_INTR_INT_C_SHIFT 11 |
| 354 | #define SD4_EMMC_TOP_INTR_INT_C_MASK 0x00000800 |
| 355 | #define SD4_EMMC_TOP_INTR_INT_B_SHIFT 10 |
| 356 | #define SD4_EMMC_TOP_INTR_INT_B_MASK 0x00000400 |
| 357 | #define SD4_EMMC_TOP_INTR_INT_A_SHIFT 9 |
| 358 | #define SD4_EMMC_TOP_INTR_INT_A_MASK 0x00000200 |
| 359 | #define SD4_EMMC_TOP_INTR_CRDIRQ_SHIFT 8 |
| 360 | #define SD4_EMMC_TOP_INTR_CRDIRQ_MASK 0x00000100 |
| 361 | #define SD4_EMMC_TOP_INTR_CRDRMV_SHIFT 7 |
| 362 | #define SD4_EMMC_TOP_INTR_CRDRMV_MASK 0x00000080 |
| 363 | #define SD4_EMMC_TOP_INTR_CRDINS_SHIFT 6 |
| 364 | #define SD4_EMMC_TOP_INTR_CRDINS_MASK 0x00000040 |
| 365 | #define SD4_EMMC_TOP_INTR_BRRDY_SHIFT 5 |
| 366 | #define SD4_EMMC_TOP_INTR_BRRDY_MASK 0x00000020 |
| 367 | #define SD4_EMMC_TOP_INTR_BWRDY_SHIFT 4 |
| 368 | #define SD4_EMMC_TOP_INTR_BWRDY_MASK 0x00000010 |
| 369 | #define SD4_EMMC_TOP_INTR_DMAIRQ_SHIFT 3 |
| 370 | #define SD4_EMMC_TOP_INTR_DMAIRQ_MASK 0x00000008 |
| 371 | #define SD4_EMMC_TOP_INTR_BLKENT_SHIFT 2 |
| 372 | #define SD4_EMMC_TOP_INTR_BLKENT_MASK 0x00000004 |
| 373 | #define SD4_EMMC_TOP_INTR_TXDONE_SHIFT 1 |
| 374 | #define SD4_EMMC_TOP_INTR_TXDONE_MASK 0x00000002 |
| 375 | #define SD4_EMMC_TOP_INTR_CMDDONE_SHIFT 0 |
| 376 | #define SD4_EMMC_TOP_INTR_CMDDONE_MASK 0x00000001 |
| 377 | |
| 378 | #define SD4_EMMC_TOP_INTR_SD4_OFFSET 0x00000030 |
| 379 | #define SD4_EMMC_TOP_INTR_SD4_DEFAULT 0x00000000 |
| 380 | #define SD4_EMMC_TOP_INTR_SD4_TYPE uint32_t |
| 381 | #define SD4_EMMC_TOP_INTR_SD4_RESERVED_MASK 0xF0006000 |
| 382 | #define SD4_EMMC_TOP_INTR_SD4_TRESPERR_SHIFT 27 |
| 383 | #define SD4_EMMC_TOP_INTR_SD4_TRESPERR_MASK 0x08000000 |
| 384 | #define SD4_EMMC_TOP_INTR_SD4_TUNEERR_SHIFT 26 |
| 385 | #define SD4_EMMC_TOP_INTR_SD4_TUNEERR_MASK 0x04000000 |
| 386 | #define SD4_EMMC_TOP_INTR_SD4_ADMAERR_SHIFT 25 |
| 387 | #define SD4_EMMC_TOP_INTR_SD4_ADMAERR_MASK 0x02000000 |
| 388 | #define SD4_EMMC_TOP_INTR_SD4_CMDERROR_SHIFT 24 |
| 389 | #define SD4_EMMC_TOP_INTR_SD4_CMDERROR_MASK 0x01000000 |
| 390 | #define SD4_EMMC_TOP_INTR_SD4_IERR_SHIFT 23 |
| 391 | #define SD4_EMMC_TOP_INTR_SD4_IERR_MASK 0x00800000 |
| 392 | #define SD4_EMMC_TOP_INTR_SD4_DEBERR_SHIFT 22 |
| 393 | #define SD4_EMMC_TOP_INTR_SD4_DEBERR_MASK 0x00400000 |
| 394 | #define SD4_EMMC_TOP_INTR_SD4_DCRCERR_SHIFT 21 |
| 395 | #define SD4_EMMC_TOP_INTR_SD4_DCRCERR_MASK 0x00200000 |
| 396 | #define SD4_EMMC_TOP_INTR_SD4_DTOERR_SHIFT 20 |
| 397 | #define SD4_EMMC_TOP_INTR_SD4_DTOERR_MASK 0x00100000 |
| 398 | #define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_SHIFT 19 |
| 399 | #define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_MASK 0x00080000 |
| 400 | #define SD4_EMMC_TOP_INTR_SD4_CEBERR_SHIFT 18 |
| 401 | #define SD4_EMMC_TOP_INTR_SD4_CEBERR_MASK 0x00040000 |
| 402 | #define SD4_EMMC_TOP_INTR_SD4_CCRCERR_SHIFT 17 |
| 403 | #define SD4_EMMC_TOP_INTR_SD4_CCRCERR_MASK 0x00020000 |
| 404 | #define SD4_EMMC_TOP_INTR_SD4_CTOERR_SHIFT 16 |
| 405 | #define SD4_EMMC_TOP_INTR_SD4_CTOERR_MASK 0x00010000 |
| 406 | #define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_SHIFT 15 |
| 407 | #define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_MASK 0x00008000 |
| 408 | #define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_SHIFT 12 |
| 409 | #define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_MASK 0x00001000 |
| 410 | #define SD4_EMMC_TOP_INTR_SD4_INT_C_SHIFT 11 |
| 411 | #define SD4_EMMC_TOP_INTR_SD4_INT_C_MASK 0x00000800 |
| 412 | #define SD4_EMMC_TOP_INTR_SD4_INT_B_SHIFT 10 |
| 413 | #define SD4_EMMC_TOP_INTR_SD4_INT_B_MASK 0x00000400 |
| 414 | #define SD4_EMMC_TOP_INTR_SD4_INT_A_SHIFT 9 |
| 415 | #define SD4_EMMC_TOP_INTR_SD4_INT_A_MASK 0x00000200 |
| 416 | #define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_SHIFT 8 |
| 417 | #define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_MASK 0x00000100 |
| 418 | #define SD4_EMMC_TOP_INTR_SD4_CRDRMV_SHIFT 7 |
| 419 | #define SD4_EMMC_TOP_INTR_SD4_CRDRMV_MASK 0x00000080 |
| 420 | #define SD4_EMMC_TOP_INTR_SD4_CRDINS_SHIFT 6 |
| 421 | #define SD4_EMMC_TOP_INTR_SD4_CRDINS_MASK 0x00000040 |
| 422 | #define SD4_EMMC_TOP_INTR_SD4_BRRDY_SHIFT 5 |
| 423 | #define SD4_EMMC_TOP_INTR_SD4_BRRDY_MASK 0x00000020 |
| 424 | #define SD4_EMMC_TOP_INTR_SD4_BWRDY_SHIFT 4 |
| 425 | #define SD4_EMMC_TOP_INTR_SD4_BWRDY_MASK 0x00000010 |
| 426 | #define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_SHIFT 3 |
| 427 | #define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_MASK 0x00000008 |
| 428 | #define SD4_EMMC_TOP_INTR_SD4_BLKENT_SHIFT 2 |
| 429 | #define SD4_EMMC_TOP_INTR_SD4_BLKENT_MASK 0x00000004 |
| 430 | #define SD4_EMMC_TOP_INTR_SD4_TXDONE_SHIFT 1 |
| 431 | #define SD4_EMMC_TOP_INTR_SD4_TXDONE_MASK 0x00000002 |
| 432 | #define SD4_EMMC_TOP_INTR_SD4_CMDDONE_SHIFT 0 |
| 433 | #define SD4_EMMC_TOP_INTR_SD4_CMDDONE_MASK 0x00000001 |
| 434 | |
| 435 | #define SD4_EMMC_TOP_INTREN1_OFFSET 0x00000034 |
| 436 | #define SD4_EMMC_TOP_INTREN1_DEFAULT 0x00000000 |
| 437 | #define SD4_EMMC_TOP_INTREN1_TYPE uint32_t |
| 438 | #define SD4_EMMC_TOP_INTREN1_RESERVED_MASK 0xEC000000 |
| 439 | #define SD4_EMMC_TOP_INTREN1_TRESPERREN_SHIFT 28 |
| 440 | #define SD4_EMMC_TOP_INTREN1_TRESPERREN_MASK 0x10000000 |
| 441 | #define SD4_EMMC_TOP_INTREN1_ADMAEREN_SHIFT 25 |
| 442 | #define SD4_EMMC_TOP_INTREN1_ADMAEREN_MASK 0x02000000 |
| 443 | #define SD4_EMMC_TOP_INTREN1_CMDERREN_SHIFT 24 |
| 444 | #define SD4_EMMC_TOP_INTREN1_CMDERREN_MASK 0x01000000 |
| 445 | #define SD4_EMMC_TOP_INTREN1_ILIMERREN_SHIFT 23 |
| 446 | #define SD4_EMMC_TOP_INTREN1_ILIMERREN_MASK 0x00800000 |
| 447 | #define SD4_EMMC_TOP_INTREN1_DEBERREN_SHIFT 22 |
| 448 | #define SD4_EMMC_TOP_INTREN1_DEBERREN_MASK 0x00400000 |
| 449 | #define SD4_EMMC_TOP_INTREN1_DCRCERREN_SHIFT 21 |
| 450 | #define SD4_EMMC_TOP_INTREN1_DCRCERREN_MASK 0x00200000 |
| 451 | #define SD4_EMMC_TOP_INTREN1_DTOERREN_SHIFT 20 |
| 452 | #define SD4_EMMC_TOP_INTREN1_DTOERREN_MASK 0x00100000 |
| 453 | #define SD4_EMMC_TOP_INTREN1_CIDXERREN_SHIFT 19 |
| 454 | #define SD4_EMMC_TOP_INTREN1_CIDXERREN_MASK 0x00080000 |
| 455 | #define SD4_EMMC_TOP_INTREN1_CEBERREN_SHIFT 18 |
| 456 | #define SD4_EMMC_TOP_INTREN1_CEBERREN_MASK 0x00040000 |
| 457 | #define SD4_EMMC_TOP_INTREN1_CMDCRCEN_SHIFT 17 |
| 458 | #define SD4_EMMC_TOP_INTREN1_CMDCRCEN_MASK 0x00020000 |
| 459 | #define SD4_EMMC_TOP_INTREN1_CMDTOEN_SHIFT 16 |
| 460 | #define SD4_EMMC_TOP_INTREN1_CMDTOEN_MASK 0x00010000 |
| 461 | #define SD4_EMMC_TOP_INTREN1_FIXZ_SHIFT 15 |
| 462 | #define SD4_EMMC_TOP_INTREN1_FIXZ_MASK 0x00008000 |
| 463 | #define SD4_EMMC_TOP_INTREN1_BTIRQEN_SHIFT 14 |
| 464 | #define SD4_EMMC_TOP_INTREN1_BTIRQEN_MASK 0x00004000 |
| 465 | #define SD4_EMMC_TOP_INTREN1_BTACKRXEN_SHIFT 13 |
| 466 | #define SD4_EMMC_TOP_INTREN1_BTACKRXEN_MASK 0x00002000 |
| 467 | #define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_SHIFT 12 |
| 468 | #define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_MASK 0x00001000 |
| 469 | #define SD4_EMMC_TOP_INTREN1_INT_C_EN_SHIFT 11 |
| 470 | #define SD4_EMMC_TOP_INTREN1_INT_C_EN_MASK 0x00000800 |
| 471 | #define SD4_EMMC_TOP_INTREN1_INT_B_EN_SHIFT 10 |
| 472 | #define SD4_EMMC_TOP_INTREN1_INT_B_EN_MASK 0x00000400 |
| 473 | #define SD4_EMMC_TOP_INTREN1_INT_A_EN_SHIFT 9 |
| 474 | #define SD4_EMMC_TOP_INTREN1_INT_A_EN_MASK 0x00000200 |
| 475 | #define SD4_EMMC_TOP_INTREN1_CIRQEN_SHIFT 8 |
| 476 | #define SD4_EMMC_TOP_INTREN1_CIRQEN_MASK 0x00000100 |
| 477 | #define SD4_EMMC_TOP_INTREN1_CRDRMVEN_SHIFT 7 |
| 478 | #define SD4_EMMC_TOP_INTREN1_CRDRMVEN_MASK 0x00000080 |
| 479 | #define SD4_EMMC_TOP_INTREN1_CRDINSEN_SHIFT 6 |
| 480 | #define SD4_EMMC_TOP_INTREN1_CRDINSEN_MASK 0x00000040 |
| 481 | #define SD4_EMMC_TOP_INTREN1_BUFRREN_SHIFT 5 |
| 482 | #define SD4_EMMC_TOP_INTREN1_BUFRREN_MASK 0x00000020 |
| 483 | #define SD4_EMMC_TOP_INTREN1_BUFWREN_SHIFT 4 |
| 484 | #define SD4_EMMC_TOP_INTREN1_BUFWREN_MASK 0x00000010 |
| 485 | #define SD4_EMMC_TOP_INTREN1_DMAIRQEN_SHIFT 3 |
| 486 | #define SD4_EMMC_TOP_INTREN1_DMAIRQEN_MASK 0x00000008 |
| 487 | #define SD4_EMMC_TOP_INTREN1_BLKEN_SHIFT 2 |
| 488 | #define SD4_EMMC_TOP_INTREN1_BLKEN_MASK 0x00000004 |
| 489 | #define SD4_EMMC_TOP_INTREN1_TXDONEEN_SHIFT 1 |
| 490 | #define SD4_EMMC_TOP_INTREN1_TXDONEEN_MASK 0x00000002 |
| 491 | #define SD4_EMMC_TOP_INTREN1_CMDDONEEN_SHIFT 0 |
| 492 | #define SD4_EMMC_TOP_INTREN1_CMDDONEEN_MASK 0x00000001 |
| 493 | |
| 494 | #define SD4_EMMC_TOP_INTREN1_SD4_OFFSET 0x00000034 |
| 495 | #define SD4_EMMC_TOP_INTREN1_SD4_DEFAULT 0x00000000 |
| 496 | #define SD4_EMMC_TOP_INTREN1_SD4_TYPE uint32_t |
| 497 | #define SD4_EMMC_TOP_INTREN1_SD4_RESERVED_MASK 0x00006000 |
| 498 | #define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_SHIFT 28 |
| 499 | #define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_MASK 0xF0000000 |
| 500 | #define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_SHIFT 27 |
| 501 | #define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_MASK 0x08000000 |
| 502 | #define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_SHIFT 26 |
| 503 | #define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_MASK 0x04000000 |
| 504 | #define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_SHIFT 25 |
| 505 | #define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_MASK 0x02000000 |
| 506 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_SHIFT 24 |
| 507 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_MASK 0x01000000 |
| 508 | #define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_SHIFT 23 |
| 509 | #define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_MASK 0x00800000 |
| 510 | #define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_SHIFT 22 |
| 511 | #define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_MASK 0x00400000 |
| 512 | #define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_SHIFT 21 |
| 513 | #define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_MASK 0x00200000 |
| 514 | #define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_SHIFT 20 |
| 515 | #define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_MASK 0x00100000 |
| 516 | #define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_SHIFT 19 |
| 517 | #define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_MASK 0x00080000 |
| 518 | #define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_SHIFT 18 |
| 519 | #define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_MASK 0x00040000 |
| 520 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_SHIFT 17 |
| 521 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_MASK 0x00020000 |
| 522 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_SHIFT 16 |
| 523 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_MASK 0x00010000 |
| 524 | #define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_SHIFT 15 |
| 525 | #define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_MASK 0x00008000 |
| 526 | #define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_SHIFT 12 |
| 527 | #define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_MASK 0x00001000 |
| 528 | #define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_SHIFT 11 |
| 529 | #define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_MASK 0x00000800 |
| 530 | #define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_SHIFT 10 |
| 531 | #define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_MASK 0x00000400 |
| 532 | #define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_SHIFT 9 |
| 533 | #define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_MASK 0x00000200 |
| 534 | #define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_SHIFT 8 |
| 535 | #define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_MASK 0x00000100 |
| 536 | #define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_SHIFT 7 |
| 537 | #define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_MASK 0x00000080 |
| 538 | #define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_SHIFT 6 |
| 539 | #define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_MASK 0x00000040 |
| 540 | #define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_SHIFT 5 |
| 541 | #define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_MASK 0x00000020 |
| 542 | #define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_SHIFT 4 |
| 543 | #define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_MASK 0x00000010 |
| 544 | #define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_SHIFT 3 |
| 545 | #define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_MASK 0x00000008 |
| 546 | #define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_SHIFT 2 |
| 547 | #define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_MASK 0x00000004 |
| 548 | #define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_SHIFT 1 |
| 549 | #define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_MASK 0x00000002 |
| 550 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_SHIFT 0 |
| 551 | #define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_MASK 0x00000001 |
| 552 | |
| 553 | #define SD4_EMMC_TOP_INTREN2_OFFSET 0x00000038 |
| 554 | #define SD4_EMMC_TOP_INTREN2_DEFAULT 0x00000000 |
| 555 | #define SD4_EMMC_TOP_INTREN2_TYPE uint32_t |
| 556 | #define SD4_EMMC_TOP_INTREN2_RESERVED_MASK 0xEC000000 |
| 557 | #define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_SHIFT 28 |
| 558 | #define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_MASK 0x10000000 |
| 559 | #define SD4_EMMC_TOP_INTREN2_ADMASIGEN_SHIFT 25 |
| 560 | #define SD4_EMMC_TOP_INTREN2_ADMASIGEN_MASK 0x02000000 |
| 561 | #define SD4_EMMC_TOP_INTREN2_CMDSIGEN_SHIFT 24 |
| 562 | #define SD4_EMMC_TOP_INTREN2_CMDSIGEN_MASK 0x01000000 |
| 563 | #define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_SHIFT 23 |
| 564 | #define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_MASK 0x00800000 |
| 565 | #define SD4_EMMC_TOP_INTREN2_DEBSIGEN_SHIFT 22 |
| 566 | #define SD4_EMMC_TOP_INTREN2_DEBSIGEN_MASK 0x00400000 |
| 567 | #define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_SHIFT 21 |
| 568 | #define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_MASK 0x00200000 |
| 569 | #define SD4_EMMC_TOP_INTREN2_DTOSIGEN_SHIFT 20 |
| 570 | #define SD4_EMMC_TOP_INTREN2_DTOSIGEN_MASK 0x00100000 |
| 571 | #define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_SHIFT 19 |
| 572 | #define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_MASK 0x00080000 |
| 573 | #define SD4_EMMC_TOP_INTREN2_CEBSIGEN_SHIFT 18 |
| 574 | #define SD4_EMMC_TOP_INTREN2_CEBSIGEN_MASK 0x00040000 |
| 575 | #define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_SHIFT 17 |
| 576 | #define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_MASK 0x00020000 |
| 577 | #define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_SHIFT 16 |
| 578 | #define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_MASK 0x00010000 |
| 579 | #define SD4_EMMC_TOP_INTREN2_FIXZERO_SHIFT 15 |
| 580 | #define SD4_EMMC_TOP_INTREN2_FIXZERO_MASK 0x00008000 |
| 581 | #define SD4_EMMC_TOP_INTREN2_BTIRQSEN_SHIFT 14 |
| 582 | #define SD4_EMMC_TOP_INTREN2_BTIRQSEN_MASK 0x00004000 |
| 583 | #define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_SHIFT 13 |
| 584 | #define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_MASK 0x00002000 |
| 585 | #define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_SHIFT 12 |
| 586 | #define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_MASK 0x00001000 |
| 587 | #define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_SHIFT 11 |
| 588 | #define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_MASK 0x00000800 |
| 589 | #define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_SHIFT 10 |
| 590 | #define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_MASK 0x00000400 |
| 591 | #define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_SHIFT 9 |
| 592 | #define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_MASK 0x00000200 |
| 593 | #define SD4_EMMC_TOP_INTREN2_CRDIRQEN_SHIFT 8 |
| 594 | #define SD4_EMMC_TOP_INTREN2_CRDIRQEN_MASK 0x00000100 |
| 595 | #define SD4_EMMC_TOP_INTREN2_CRDRVMEN_SHIFT 7 |
| 596 | #define SD4_EMMC_TOP_INTREN2_CRDRVMEN_MASK 0x00000080 |
| 597 | #define SD4_EMMC_TOP_INTREN2_CRDINSEN_SHIFT 6 |
| 598 | #define SD4_EMMC_TOP_INTREN2_CRDINSEN_MASK 0x00000040 |
| 599 | #define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_SHIFT 5 |
| 600 | #define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_MASK 0x00000020 |
| 601 | #define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_SHIFT 4 |
| 602 | #define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_MASK 0x00000010 |
| 603 | #define SD4_EMMC_TOP_INTREN2_DMAIRQEN_SHIFT 3 |
| 604 | #define SD4_EMMC_TOP_INTREN2_DMAIRQEN_MASK 0x00000008 |
| 605 | #define SD4_EMMC_TOP_INTREN2_BLKGAPEN_SHIFT 2 |
| 606 | #define SD4_EMMC_TOP_INTREN2_BLKGAPEN_MASK 0x00000004 |
| 607 | #define SD4_EMMC_TOP_INTREN2_TXDONE_SHIFT 1 |
| 608 | #define SD4_EMMC_TOP_INTREN2_TXDONE_MASK 0x00000002 |
| 609 | #define SD4_EMMC_TOP_INTREN2_CMDDONE_SHIFT 0 |
| 610 | #define SD4_EMMC_TOP_INTREN2_CMDDONE_MASK 0x00000001 |
| 611 | |
| 612 | #define SD4_EMMC_TOP_INTREN2_SD4_OFFSET 0x00000038 |
| 613 | #define SD4_EMMC_TOP_INTREN2_SD4_DEFAULT 0x00000000 |
| 614 | #define SD4_EMMC_TOP_INTREN2_SD4_TYPE uint32_t |
| 615 | #define SD4_EMMC_TOP_INTREN2_SD4_RESERVED_MASK 0xF0006000 |
| 616 | #define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_SHIFT 27 |
| 617 | #define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_MASK 0x08000000 |
| 618 | #define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_SHIFT 26 |
| 619 | #define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_MASK 0x04000000 |
| 620 | #define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_SHIFT 25 |
| 621 | #define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_MASK 0x02000000 |
| 622 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_SHIFT 24 |
| 623 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_MASK 0x01000000 |
| 624 | #define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_SHIFT 23 |
| 625 | #define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_MASK 0x00800000 |
| 626 | #define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_SHIFT 22 |
| 627 | #define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_MASK 0x00400000 |
| 628 | #define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_SHIFT 21 |
| 629 | #define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_MASK 0x00200000 |
| 630 | #define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_SHIFT 20 |
| 631 | #define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_MASK 0x00100000 |
| 632 | #define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_SHIFT 19 |
| 633 | #define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_MASK 0x00080000 |
| 634 | #define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_SHIFT 18 |
| 635 | #define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_MASK 0x00040000 |
| 636 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_SHIFT 17 |
| 637 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_MASK 0x00020000 |
| 638 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_SHIFT 16 |
| 639 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_MASK 0x00010000 |
| 640 | #define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_SHIFT 15 |
| 641 | #define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_MASK 0x00008000 |
| 642 | #define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_SHIFT 12 |
| 643 | #define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_MASK 0x00001000 |
| 644 | #define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_SHIFT 11 |
| 645 | #define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_MASK 0x00000800 |
| 646 | #define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_SHIFT 10 |
| 647 | #define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_MASK 0x00000400 |
| 648 | #define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_SHIFT 9 |
| 649 | #define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_MASK 0x00000200 |
| 650 | #define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_SHIFT 8 |
| 651 | #define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_MASK 0x00000100 |
| 652 | #define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_SHIFT 7 |
| 653 | #define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_MASK 0x00000080 |
| 654 | #define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_SHIFT 6 |
| 655 | #define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_MASK 0x00000040 |
| 656 | #define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_SHIFT 5 |
| 657 | #define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_MASK 0x00000020 |
| 658 | #define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_SHIFT 4 |
| 659 | #define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_MASK 0x00000010 |
| 660 | #define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_SHIFT 3 |
| 661 | #define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_MASK 0x00000008 |
| 662 | #define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_SHIFT 2 |
| 663 | #define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_MASK 0x00000004 |
| 664 | #define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_SHIFT 1 |
| 665 | #define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_MASK 0x00000002 |
| 666 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_SHIFT 0 |
| 667 | #define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_MASK 0x00000001 |
| 668 | |
| 669 | #define SD4_EMMC_TOP_ERRSTAT_OFFSET 0x0000003C |
| 670 | #define SD4_EMMC_TOP_ERRSTAT_DEFAULT 0x00000000 |
| 671 | #define SD4_EMMC_TOP_ERRSTAT_TYPE uint32_t |
| 672 | #define SD4_EMMC_TOP_ERRSTAT_RESERVED_MASK 0x3F00FF60 |
| 673 | #define SD4_EMMC_TOP_ERRSTAT_PRESETEN_SHIFT 31 |
| 674 | #define SD4_EMMC_TOP_ERRSTAT_PRESETEN_MASK 0x80000000 |
| 675 | #define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_SHIFT 30 |
| 676 | #define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_MASK 0x40000000 |
| 677 | #define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_SHIFT 23 |
| 678 | #define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_MASK 0x00800000 |
| 679 | #define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_SHIFT 22 |
| 680 | #define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_MASK 0x00400000 |
| 681 | #define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_SHIFT 20 |
| 682 | #define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_MASK 0x00300000 |
| 683 | #define SD4_EMMC_TOP_ERRSTAT_EN1P8V_SHIFT 19 |
| 684 | #define SD4_EMMC_TOP_ERRSTAT_EN1P8V_MASK 0x00080000 |
| 685 | #define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_SHIFT 16 |
| 686 | #define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_MASK 0x00070000 |
| 687 | #define SD4_EMMC_TOP_ERRSTAT_NOCMD_SHIFT 7 |
| 688 | #define SD4_EMMC_TOP_ERRSTAT_NOCMD_MASK 0x00000080 |
| 689 | #define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_SHIFT 4 |
| 690 | #define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_MASK 0x00000010 |
| 691 | #define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_SHIFT 3 |
| 692 | #define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_MASK 0x00000008 |
| 693 | #define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_SHIFT 2 |
| 694 | #define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_MASK 0x00000004 |
| 695 | #define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_SHIFT 1 |
| 696 | #define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_MASK 0x00000002 |
| 697 | #define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_SHIFT 0 |
| 698 | #define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_MASK 0x00000001 |
| 699 | |
| 700 | #define SD4_EMMC_TOP_ERRSTAT_SD4_OFFSET 0x0000003C |
| 701 | #define SD4_EMMC_TOP_ERRSTAT_SD4_DEFAULT 0x00000000 |
| 702 | #define SD4_EMMC_TOP_ERRSTAT_SD4_TYPE uint32_t |
| 703 | #define SD4_EMMC_TOP_ERRSTAT_SD4_RESERVED_MASK 0x0E00FF40 |
| 704 | #define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_SHIFT 31 |
| 705 | #define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_MASK 0x80000000 |
| 706 | #define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_SHIFT 30 |
| 707 | #define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_MASK 0x40000000 |
| 708 | #define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_SHIFT 29 |
| 709 | #define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_MASK 0x20000000 |
| 710 | #define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_SHIFT 28 |
| 711 | #define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_MASK 0x10000000 |
| 712 | #define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_SHIFT 24 |
| 713 | #define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_MASK 0x01000000 |
| 714 | #define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_SHIFT 23 |
| 715 | #define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_MASK 0x00800000 |
| 716 | #define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_SHIFT 22 |
| 717 | #define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_MASK 0x00400000 |
| 718 | #define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_SHIFT 20 |
| 719 | #define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_MASK 0x00300000 |
| 720 | #define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_SHIFT 19 |
| 721 | #define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_MASK 0x00080000 |
| 722 | #define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_SHIFT 16 |
| 723 | #define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_MASK 0x00070000 |
| 724 | #define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_SHIFT 7 |
| 725 | #define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_MASK 0x00000080 |
| 726 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_SHIFT 5 |
| 727 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_MASK 0x00000020 |
| 728 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_SHIFT 4 |
| 729 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_MASK 0x00000010 |
| 730 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_SHIFT 3 |
| 731 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_MASK 0x00000008 |
| 732 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_SHIFT 2 |
| 733 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_MASK 0x00000004 |
| 734 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_SHIFT 1 |
| 735 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_MASK 0x00000002 |
| 736 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_SHIFT 0 |
| 737 | #define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_MASK 0x00000001 |
| 738 | |
| 739 | #define SD4_EMMC_TOP_CAPABILITIES1_OFFSET 0x00000040 |
| 740 | #define SD4_EMMC_TOP_CAPABILITIES1_DEFAULT 0x17EFD0B0 |
| 741 | #define SD4_EMMC_TOP_CAPABILITIES1_TYPE uint32_t |
| 742 | #define SD4_EMMC_TOP_CAPABILITIES1_RESERVED_MASK 0x08100040 |
| 743 | #define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_SHIFT 30 |
| 744 | #define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_MASK 0xC0000000 |
| 745 | #define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_SHIFT 29 |
| 746 | #define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_MASK 0x20000000 |
| 747 | #define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_SHIFT 28 |
| 748 | #define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_MASK 0x10000000 |
| 749 | #define SD4_EMMC_TOP_CAPABILITIES1_V18_SHIFT 26 |
| 750 | #define SD4_EMMC_TOP_CAPABILITIES1_V18_MASK 0x04000000 |
| 751 | #define SD4_EMMC_TOP_CAPABILITIES1_V3_SHIFT 25 |
| 752 | #define SD4_EMMC_TOP_CAPABILITIES1_V3_MASK 0x02000000 |
| 753 | #define SD4_EMMC_TOP_CAPABILITIES1_V33_SHIFT 24 |
| 754 | #define SD4_EMMC_TOP_CAPABILITIES1_V33_MASK 0x01000000 |
| 755 | #define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_SHIFT 23 |
| 756 | #define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_MASK 0x00800000 |
| 757 | #define SD4_EMMC_TOP_CAPABILITIES1_SDMA_SHIFT 22 |
| 758 | #define SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK 0x00400000 |
| 759 | #define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_SHIFT 21 |
| 760 | #define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_MASK 0x00200000 |
| 761 | #define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_SHIFT 19 |
| 762 | #define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK 0x00080000 |
| 763 | #define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_SHIFT 18 |
| 764 | #define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_MASK 0x00040000 |
| 765 | #define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_SHIFT 16 |
| 766 | #define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_MASK 0x00030000 |
| 767 | #define SD4_EMMC_TOP_CAPABILITIES1_BCLK_SHIFT 8 |
| 768 | #define SD4_EMMC_TOP_CAPABILITIES1_BCLK_MASK 0x0000FF00 |
| 769 | #define SD4_EMMC_TOP_CAPABILITIES1_TOUT_SHIFT 7 |
| 770 | #define SD4_EMMC_TOP_CAPABILITIES1_TOUT_MASK 0x00000080 |
| 771 | #define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_SHIFT 0 |
| 772 | #define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_MASK 0x0000003F |
| 773 | |
| 774 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_OFFSET 0x00000040 |
| 775 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_DEFAULT 0x10E934B4 |
| 776 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_TYPE uint32_t |
| 777 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_RESERVED_MASK 0x08100040 |
| 778 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_SHIFT 30 |
| 779 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_MASK 0xC0000000 |
| 780 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_SHIFT 29 |
| 781 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_MASK 0x20000000 |
| 782 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_SHIFT 28 |
| 783 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_MASK 0x10000000 |
| 784 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_SHIFT 26 |
| 785 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_MASK 0x04000000 |
| 786 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_SHIFT 25 |
| 787 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_MASK 0x02000000 |
| 788 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_SHIFT 24 |
| 789 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_MASK 0x01000000 |
| 790 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_SHIFT 23 |
| 791 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_MASK 0x00800000 |
| 792 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_SHIFT 22 |
| 793 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_MASK 0x00400000 |
| 794 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_SHIFT 21 |
| 795 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_MASK 0x00200000 |
| 796 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_SHIFT 19 |
| 797 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_MASK 0x00080000 |
| 798 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_SHIFT 18 |
| 799 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_MASK 0x00040000 |
| 800 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_SHIFT 16 |
| 801 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_MASK 0x00030000 |
| 802 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_SHIFT 8 |
| 803 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_MASK 0x0000FF00 |
| 804 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_SHIFT 7 |
| 805 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_MASK 0x00000080 |
| 806 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_SHIFT 0 |
| 807 | #define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_MASK 0x0000003F |
| 808 | |
| 809 | #define SD4_EMMC_TOP_CAPABILITIES2_OFFSET 0x00000044 |
| 810 | #define SD4_EMMC_TOP_CAPABILITIES2_DEFAULT 0x03002177 |
| 811 | #define SD4_EMMC_TOP_CAPABILITIES2_TYPE uint32_t |
| 812 | #define SD4_EMMC_TOP_CAPABILITIES2_RESERVED_MASK 0xFC001088 |
| 813 | #define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_SHIFT 25 |
| 814 | #define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_MASK 0x02000000 |
| 815 | #define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_SHIFT 24 |
| 816 | #define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_MASK 0x01000000 |
| 817 | #define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_SHIFT 16 |
| 818 | #define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_MASK 0x00FF0000 |
| 819 | #define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_SHIFT 14 |
| 820 | #define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_MASK 0x0000C000 |
| 821 | #define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_SHIFT 13 |
| 822 | #define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_MASK 0x00002000 |
| 823 | #define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_SHIFT 8 |
| 824 | #define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_MASK 0x00000F00 |
| 825 | #define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_SHIFT 6 |
| 826 | #define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_MASK 0x00000040 |
| 827 | #define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_SHIFT 5 |
| 828 | #define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_MASK 0x00000020 |
| 829 | #define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_SHIFT 4 |
| 830 | #define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_MASK 0x00000010 |
| 831 | #define SD4_EMMC_TOP_CAPABILITIES2_DDR50_SHIFT 2 |
| 832 | #define SD4_EMMC_TOP_CAPABILITIES2_DDR50_MASK 0x00000004 |
| 833 | #define SD4_EMMC_TOP_CAPABILITIES2_SDR104_SHIFT 1 |
| 834 | #define SD4_EMMC_TOP_CAPABILITIES2_SDR104_MASK 0x00000002 |
| 835 | #define SD4_EMMC_TOP_CAPABILITIES2_SDR50_SHIFT 0 |
| 836 | #define SD4_EMMC_TOP_CAPABILITIES2_SDR50_MASK 0x00000001 |
| 837 | |
| 838 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_OFFSET 0x00000044 |
| 839 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DEFAULT 0x10000064 |
| 840 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_TYPE uint32_t |
| 841 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_RESERVED_MASK 0xE7001080 |
| 842 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_SHIFT 28 |
| 843 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_MASK 0x10000000 |
| 844 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_SHIFT 27 |
| 845 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_MASK 0x08000000 |
| 846 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_SHIFT 16 |
| 847 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_MASK 0x00FF0000 |
| 848 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_SHIFT 14 |
| 849 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_MASK 0x0000C000 |
| 850 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_SHIFT 13 |
| 851 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_MASK 0x00002000 |
| 852 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_SHIFT 8 |
| 853 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_MASK 0x00000F00 |
| 854 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_SHIFT 6 |
| 855 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_MASK 0x00000040 |
| 856 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_SHIFT 5 |
| 857 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_MASK 0x00000020 |
| 858 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_SHIFT 4 |
| 859 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_MASK 0x00000010 |
| 860 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_SHIFT 3 |
| 861 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_MASK 0x00000008 |
| 862 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_SHIFT 2 |
| 863 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_MASK 0x00000004 |
| 864 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_SHIFT 1 |
| 865 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_MASK 0x00000002 |
| 866 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_SHIFT 0 |
| 867 | #define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_MASK 0x00000001 |
| 868 | |
| 869 | #define SD4_EMMC_TOP_MAX_A1_OFFSET 0x00000048 |
| 870 | #define SD4_EMMC_TOP_MAX_A1_DEFAULT 0x00000001 |
| 871 | #define SD4_EMMC_TOP_MAX_A1_TYPE uint32_t |
| 872 | #define SD4_EMMC_TOP_MAX_A1_RESERVED_MASK 0xFF000000 |
| 873 | #define SD4_EMMC_TOP_MAX_A1_MAXA18_SHIFT 16 |
| 874 | #define SD4_EMMC_TOP_MAX_A1_MAXA18_MASK 0x00FF0000 |
| 875 | #define SD4_EMMC_TOP_MAX_A1_MAXA30_SHIFT 8 |
| 876 | #define SD4_EMMC_TOP_MAX_A1_MAXA30_MASK 0x0000FF00 |
| 877 | #define SD4_EMMC_TOP_MAX_A1_MAXA33_SHIFT 0 |
| 878 | #define SD4_EMMC_TOP_MAX_A1_MAXA33_MASK 0x000000FF |
| 879 | |
| 880 | #define SD4_EMMC_TOP_MAX_A2_OFFSET 0x0000004C |
| 881 | #define SD4_EMMC_TOP_MAX_A2_DEFAULT 0x00000000 |
| 882 | #define SD4_EMMC_TOP_MAX_A2_TYPE uint32_t |
| 883 | #define SD4_EMMC_TOP_MAX_A2_RESERVED_MASK 0xFFFFFFFF |
| 884 | |
| 885 | #define SD4_EMMC_TOP_MAX_A2_SD4_OFFSET 0x0000004C |
| 886 | #define SD4_EMMC_TOP_MAX_A2_SD4_DEFAULT 0x00000001 |
| 887 | #define SD4_EMMC_TOP_MAX_A2_SD4_TYPE uint32_t |
| 888 | #define SD4_EMMC_TOP_MAX_A2_SD4_RESERVED_MASK 0xFFFFFF00 |
| 889 | #define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_SHIFT 0 |
| 890 | #define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_MASK 0x000000FF |
| 891 | |
| 892 | #define SD4_EMMC_TOP_CMDENTSTAT_OFFSET 0x00000050 |
| 893 | #define SD4_EMMC_TOP_CMDENTSTAT_DEFAULT 0x00000000 |
| 894 | #define SD4_EMMC_TOP_CMDENTSTAT_TYPE uint32_t |
| 895 | #define SD4_EMMC_TOP_CMDENTSTAT_RESERVED_MASK 0x2C00FF60 |
| 896 | #define SD4_EMMC_TOP_CMDENTSTAT_VSES_SHIFT 30 |
| 897 | #define SD4_EMMC_TOP_CMDENTSTAT_VSES_MASK 0xC0000000 |
| 898 | #define SD4_EMMC_TOP_CMDENTSTAT_TRERR_SHIFT 28 |
| 899 | #define SD4_EMMC_TOP_CMDENTSTAT_TRERR_MASK 0x10000000 |
| 900 | #define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_SHIFT 25 |
| 901 | #define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_MASK 0x02000000 |
| 902 | #define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_SHIFT 24 |
| 903 | #define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_MASK 0x01000000 |
| 904 | #define SD4_EMMC_TOP_CMDENTSTAT_ILERR_SHIFT 23 |
| 905 | #define SD4_EMMC_TOP_CMDENTSTAT_ILERR_MASK 0x00800000 |
| 906 | #define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_SHIFT 22 |
| 907 | #define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_MASK 0x00400000 |
| 908 | #define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_SHIFT 21 |
| 909 | #define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_MASK 0x00200000 |
| 910 | #define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_SHIFT 20 |
| 911 | #define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_MASK 0x00100000 |
| 912 | #define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_SHIFT 19 |
| 913 | #define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_MASK 0x00080000 |
| 914 | #define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_SHIFT 18 |
| 915 | #define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_MASK 0x00040000 |
| 916 | #define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_SHIFT 17 |
| 917 | #define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_MASK 0x00020000 |
| 918 | #define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_SHIFT 16 |
| 919 | #define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_MASK 0x00010000 |
| 920 | #define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_SHIFT 7 |
| 921 | #define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_MASK 0x00000080 |
| 922 | #define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_SHIFT 4 |
| 923 | #define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_MASK 0x00000010 |
| 924 | #define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_SHIFT 3 |
| 925 | #define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_MASK 0x00000008 |
| 926 | #define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_SHIFT 2 |
| 927 | #define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_MASK 0x00000004 |
| 928 | #define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_SHIFT 1 |
| 929 | #define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_MASK 0x00000002 |
| 930 | #define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_SHIFT 0 |
| 931 | #define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_MASK 0x00000001 |
| 932 | |
| 933 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_OFFSET 0x00000050 |
| 934 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DEFAULT 0x00000000 |
| 935 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TYPE uint32_t |
| 936 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESERVED_MASK 0x0000FF40 |
| 937 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_SHIFT 28 |
| 938 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_MASK 0xF0000000 |
| 939 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_SHIFT 27 |
| 940 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_MASK 0x08000000 |
| 941 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_SHIFT 26 |
| 942 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_MASK 0x04000000 |
| 943 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_SHIFT 25 |
| 944 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_MASK 0x02000000 |
| 945 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_SHIFT 24 |
| 946 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_MASK 0x01000000 |
| 947 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_SHIFT 23 |
| 948 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_MASK 0x00800000 |
| 949 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_SHIFT 22 |
| 950 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_MASK 0x00400000 |
| 951 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_SHIFT 21 |
| 952 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_MASK 0x00200000 |
| 953 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_SHIFT 20 |
| 954 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_MASK 0x00100000 |
| 955 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_SHIFT 19 |
| 956 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_MASK 0x00080000 |
| 957 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_SHIFT 18 |
| 958 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_MASK 0x00040000 |
| 959 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_SHIFT 17 |
| 960 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_MASK 0x00020000 |
| 961 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_SHIFT 16 |
| 962 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_MASK 0x00010000 |
| 963 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_SHIFT 7 |
| 964 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_MASK 0x00000080 |
| 965 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_SHIFT 5 |
| 966 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_MASK 0x00000020 |
| 967 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_SHIFT 4 |
| 968 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_MASK 0x00000010 |
| 969 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_SHIFT 3 |
| 970 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_MASK 0x00000008 |
| 971 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_SHIFT 2 |
| 972 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_MASK 0x00000004 |
| 973 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_SHIFT 1 |
| 974 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_MASK 0x00000002 |
| 975 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_SHIFT 0 |
| 976 | #define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_MASK 0x00000001 |
| 977 | |
| 978 | #define SD4_EMMC_TOP_ADMAERR_OFFSET 0x00000054 |
| 979 | #define SD4_EMMC_TOP_ADMAERR_DEFAULT 0x00000000 |
| 980 | #define SD4_EMMC_TOP_ADMAERR_TYPE uint32_t |
| 981 | #define SD4_EMMC_TOP_ADMAERR_RESERVED_MASK 0xFFFFFFF8 |
| 982 | #define SD4_EMMC_TOP_ADMAERR_ADMALERR_SHIFT 2 |
| 983 | #define SD4_EMMC_TOP_ADMAERR_ADMALERR_MASK 0x00000004 |
| 984 | #define SD4_EMMC_TOP_ADMAERR_ADMAERR_SHIFT 0 |
| 985 | #define SD4_EMMC_TOP_ADMAERR_ADMAERR_MASK 0x00000003 |
| 986 | |
| 987 | #define SD4_EMMC_TOP_ADMAADDR0_OFFSET 0x00000058 |
| 988 | #define SD4_EMMC_TOP_ADMAADDR0_DEFAULT 0x00000000 |
| 989 | #define SD4_EMMC_TOP_ADMAADDR0_TYPE uint32_t |
| 990 | #define SD4_EMMC_TOP_ADMAADDR0_RESERVED_MASK 0x00000000 |
| 991 | #define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_SHIFT 0 |
| 992 | #define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_MASK 0xFFFFFFFF |
| 993 | |
| 994 | #define SD4_EMMC_TOP_ADMAADDR1_OFFSET 0x0000005C |
| 995 | #define SD4_EMMC_TOP_ADMAADDR1_DEFAULT 0x00000000 |
| 996 | #define SD4_EMMC_TOP_ADMAADDR1_TYPE uint32_t |
| 997 | #define SD4_EMMC_TOP_ADMAADDR1_RESERVED_MASK 0x00000000 |
| 998 | #define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_SHIFT 0 |
| 999 | #define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_MASK 0xFFFFFFFF |
| 1000 | |
| 1001 | #define SD4_EMMC_TOP_PRESETVAL1_OFFSET 0x00000060 |
| 1002 | #define SD4_EMMC_TOP_PRESETVAL1_DEFAULT 0x00000000 |
| 1003 | #define SD4_EMMC_TOP_PRESETVAL1_TYPE uint32_t |
| 1004 | #define SD4_EMMC_TOP_PRESETVAL1_RESERVED_MASK 0x38003800 |
| 1005 | #define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_SHIFT 30 |
| 1006 | #define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_MASK 0xC0000000 |
| 1007 | #define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_SHIFT 26 |
| 1008 | #define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_MASK 0x04000000 |
| 1009 | #define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_SHIFT 16 |
| 1010 | #define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_MASK 0x03FF0000 |
| 1011 | #define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_SHIFT 14 |
| 1012 | #define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_MASK 0x0000C000 |
| 1013 | #define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_SHIFT 10 |
| 1014 | #define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_MASK 0x00000400 |
| 1015 | #define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_SHIFT 0 |
| 1016 | #define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_MASK 0x000003FF |
| 1017 | |
| 1018 | #define SD4_EMMC_TOP_PRESETVAL2_OFFSET 0x00000064 |
| 1019 | #define SD4_EMMC_TOP_PRESETVAL2_DEFAULT 0x00000000 |
| 1020 | #define SD4_EMMC_TOP_PRESETVAL2_TYPE uint32_t |
| 1021 | #define SD4_EMMC_TOP_PRESETVAL2_RESERVED_MASK 0x38003800 |
| 1022 | #define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_SHIFT 30 |
| 1023 | #define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_MASK 0xC0000000 |
| 1024 | #define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_SHIFT 26 |
| 1025 | #define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_MASK 0x04000000 |
| 1026 | #define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_SHIFT 16 |
| 1027 | #define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_MASK 0x03FF0000 |
| 1028 | #define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_SHIFT 14 |
| 1029 | #define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_MASK 0x0000C000 |
| 1030 | #define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_SHIFT 10 |
| 1031 | #define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_MASK 0x00000400 |
| 1032 | #define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_SHIFT 0 |
| 1033 | #define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_MASK 0x000003FF |
| 1034 | |
| 1035 | #define SD4_EMMC_TOP_PRESETVAL3_OFFSET 0x00000068 |
| 1036 | #define SD4_EMMC_TOP_PRESETVAL3_DEFAULT 0x00000000 |
| 1037 | #define SD4_EMMC_TOP_PRESETVAL3_TYPE uint32_t |
| 1038 | #define SD4_EMMC_TOP_PRESETVAL3_RESERVED_MASK 0x38003800 |
| 1039 | #define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_SHIFT 30 |
| 1040 | #define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_MASK 0xC0000000 |
| 1041 | #define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_SHIFT 26 |
| 1042 | #define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_MASK 0x04000000 |
| 1043 | #define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_SHIFT 16 |
| 1044 | #define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_MASK 0x03FF0000 |
| 1045 | #define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_SHIFT 14 |
| 1046 | #define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_MASK 0x0000C000 |
| 1047 | #define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_SHIFT 10 |
| 1048 | #define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_MASK 0x00000400 |
| 1049 | #define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_SHIFT 0 |
| 1050 | #define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_MASK 0x000003FF |
| 1051 | |
| 1052 | #define SD4_EMMC_TOP_PRESETVAL4_OFFSET 0x0000006C |
| 1053 | #define SD4_EMMC_TOP_PRESETVAL4_DEFAULT 0x00000000 |
| 1054 | #define SD4_EMMC_TOP_PRESETVAL4_TYPE uint32_t |
| 1055 | #define SD4_EMMC_TOP_PRESETVAL4_RESERVED_MASK 0x38003800 |
| 1056 | #define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_SHIFT 30 |
| 1057 | #define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_MASK 0xC0000000 |
| 1058 | #define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_SHIFT 26 |
| 1059 | #define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_MASK 0x04000000 |
| 1060 | #define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_SHIFT 16 |
| 1061 | #define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_MASK 0x03FF0000 |
| 1062 | #define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_SHIFT 14 |
| 1063 | #define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_MASK 0x0000C000 |
| 1064 | #define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_SHIFT 10 |
| 1065 | #define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_MASK 0x00000400 |
| 1066 | #define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_SHIFT 0 |
| 1067 | #define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_MASK 0x000003FF |
| 1068 | |
| 1069 | #define SD4_EMMC_TOP_BOOTTIMEOUT_OFFSET 0x00000070 |
| 1070 | #define SD4_EMMC_TOP_BOOTTIMEOUT_DEFAULT 0x00000000 |
| 1071 | #define SD4_EMMC_TOP_BOOTTIMEOUT_TYPE uint32_t |
| 1072 | #define SD4_EMMC_TOP_BOOTTIMEOUT_RESERVED_MASK 0x00000000 |
| 1073 | #define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_SHIFT 0 |
| 1074 | #define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_MASK 0xFFFFFFFF |
| 1075 | |
| 1076 | #define SD4_EMMC_TOP_DBGSEL_OFFSET 0x00000074 |
| 1077 | #define SD4_EMMC_TOP_DBGSEL_DEFAULT 0x00000000 |
| 1078 | #define SD4_EMMC_TOP_DBGSEL_TYPE uint32_t |
| 1079 | #define SD4_EMMC_TOP_DBGSEL_RESERVED_MASK 0xFFFFFFFE |
| 1080 | #define SD4_EMMC_TOP_DBGSEL_DBGSEL_SHIFT 0 |
| 1081 | #define SD4_EMMC_TOP_DBGSEL_DBGSEL_MASK 0x00000001 |
| 1082 | |
| 1083 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_OFFSET 0x00000074 |
| 1084 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_DEFAULT 0x00000000 |
| 1085 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_TYPE uint32_t |
| 1086 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_RESERVED_MASK 0xFFFF3800 |
| 1087 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_SHIFT 14 |
| 1088 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_MASK 0x0000C000 |
| 1089 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_SHIFT 10 |
| 1090 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_MASK 0x00000400 |
| 1091 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_SHIFT 0 |
| 1092 | #define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_MASK 0x000003FF |
| 1093 | |
| 1094 | #define SD4_EMMC_TOP_HCVERSIRQ_OFFSET 0x000000FC |
| 1095 | #define SD4_EMMC_TOP_HCVERSIRQ_DEFAULT 0x10020000 |
| 1096 | #define SD4_EMMC_TOP_HCVERSIRQ_TYPE uint32_t |
| 1097 | #define SD4_EMMC_TOP_HCVERSIRQ_RESERVED_MASK 0x0000FF00 |
| 1098 | #define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_SHIFT 24 |
| 1099 | #define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_MASK 0xFF000000 |
| 1100 | #define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_SHIFT 16 |
| 1101 | #define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_MASK 0x00FF0000 |
| 1102 | #define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_SHIFT 0 |
| 1103 | #define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_MASK 0x000000FF |
| 1104 | |
| 1105 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_OFFSET 0x000000FC |
| 1106 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_DEFAULT 0x01030000 |
| 1107 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_TYPE uint32_t |
| 1108 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_RESERVED_MASK 0x0000FF00 |
| 1109 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_SHIFT 24 |
| 1110 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_MASK 0xFF000000 |
| 1111 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_SHIFT 16 |
| 1112 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_MASK 0x00FF0000 |
| 1113 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_SHIFT 0 |
| 1114 | #define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_MASK 0x000000FF |
| 1115 | |
| 1116 | #endif /* BRCM_RDB_SD4_EMMC_TOP_H */ |