blob: 221665471ebc9fcdcb1324b7e850c69a4fa5db43 [file] [log] [blame]
Samuel Holland74383202017-08-12 04:07:39 -05001#
2# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
9AW_PLAT := plat/allwinner
10
11PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
12 -Iinclude/plat/arm/common/aarch64 \
13 -I${AW_PLAT}/common/include \
14 -I${AW_PLAT}/${PLAT}/include
15
16PLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \
17 drivers/ti/uart/${ARCH}/16550_console.S \
18 ${XLAT_TABLES_LIB_SRCS} \
19 ${AW_PLAT}/common/plat_helpers.S \
20 ${AW_PLAT}/common/sunxi_common.c
21
22BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
23 drivers/arm/gic/v2/gicv2_helpers.c \
24 drivers/arm/gic/v2/gicv2_main.c \
25 drivers/delay_timer/delay_timer.c \
26 drivers/delay_timer/generic_delay_timer.c \
27 lib/cpus/${ARCH}/cortex_a53.S \
28 plat/common/plat_gicv2.c \
29 plat/common/plat_psci_common.c \
30 ${AW_PLAT}/common/sunxi_bl31_setup.c \
Samuel Holland321c0ab2017-08-12 04:07:39 -050031 ${AW_PLAT}/common/sunxi_cpu_ops.c \
Samuel Holland74383202017-08-12 04:07:39 -050032 ${AW_PLAT}/common/sunxi_pm.c \
Icenowy Zheng7508bef2018-07-21 20:41:12 +080033 ${AW_PLAT}/sun50i_a64/sunxi_power.c \
Andre Przywara13815472018-06-01 02:01:39 +010034 ${AW_PLAT}/common/sunxi_security.c \
Samuel Holland74383202017-08-12 04:07:39 -050035 ${AW_PLAT}/common/sunxi_topology.c
36
37# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
38COLD_BOOT_SINGLE_CPU := 1
39
40# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
41ERRATA_A53_835769 := 1
42ERRATA_A53_843419 := 1
43ERRATA_A53_855873 := 1
44
Samuel Holland74383202017-08-12 04:07:39 -050045MULTI_CONSOLE_API := 1
46
Samuel Holland74383202017-08-12 04:07:39 -050047# The reset vector can be changed for each CPU.
48PROGRAMMABLE_RESET_ADDRESS := 1
49
50# Allow mapping read-only data as execute-never.
51SEPARATE_CODE_AND_RODATA := 1
52
53# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
54RESET_TO_BL31 := 1