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Varun Wadekarb3741032017-09-25 13:27:45 -07001/*
steven kao05ee5822018-01-02 19:07:00 -08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar2909fa32020-01-09 08:52:10 -08003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb3741032017-09-25 13:27:45 -07004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Varun Wadekar2909fa32020-01-09 08:52:10 -08008#ifndef BPMP_IPC_H
9#define BPMP_IPC_H
Varun Wadekarb3741032017-09-25 13:27:45 -070010
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000011#include <lib/utils_def.h>
Varun Wadekarb3741032017-09-25 13:27:45 -070012#include <stdbool.h>
13#include <stdint.h>
Varun Wadekarb3741032017-09-25 13:27:45 -070014
15/**
16 * Currently supported reset identifiers
17 */
18#define TEGRA_RESET_ID_XUSB_PADCTL U(114)
19#define TEGRA_RESET_ID_GPCDMA U(70)
20
21/**
22 * Function to initialise the IPC with the bpmp
23 */
24int32_t tegra_bpmp_ipc_init(void);
25
26/**
27 * Handler to reset a module
28 */
29int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id);
30
steven kao05ee5822018-01-02 19:07:00 -080031/**
32 * Handler to enable clock to a module. Only SE device is
33 * supported for now.
34 */
35int tegra_bpmp_ipc_enable_clock(uint32_t clk_id);
36
37/**
38 * Handler to disable clock to a module. Only SE device is
39 * supported for now.
40 */
41int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
42
Varun Wadekar2909fa32020-01-09 08:52:10 -080043#endif /* BPMP_IPC_H */