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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7cf57d72018-05-17 09:36:38 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Varun Wadekarb7b45752015-12-28 14:55:41 -08008#include <arch_helpers.h>
Varun Wadekarf07d6de2018-02-27 14:33:57 -08009#include <assert.h>
Sam Payne71ce6ed2017-05-08 12:42:49 -070010#include <cortex_a57.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
Varun Wadekar4538bfc2019-01-02 17:53:15 -080012#include <common/debug.h>
13#include <common/interrupt_props.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <drivers/console.h>
15#include <lib/xlat_tables/xlat_tables_v2.h>
Varun Wadekar4538bfc2019-01-02 17:53:15 -080016#include <drivers/arm/gic_common.h>
17#include <drivers/arm/gicv2.h>
18#include <bl31/interrupt_mgmt.h>
19
20#include <bpmp.h>
21#include <flowctrl.h>
Varun Wadekar6e29d4d2018-03-07 11:13:58 -080022#include <memctrl.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000023#include <plat/common/platform.h>
Marvin Hsu21eea972017-04-11 11:00:48 +080024#include <security_engine.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053025#include <tegra_def.h>
Marvin Hsu21eea972017-04-11 11:00:48 +080026#include <tegra_platform.h>
Varun Wadekarb7b45752015-12-28 14:55:41 -080027#include <tegra_private.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053028
Varun Wadekarb316e242015-05-19 16:48:04 +053029/* sets of MMIO ranges setup */
30#define MMIO_RANGE_0_ADDR 0x50000000
31#define MMIO_RANGE_1_ADDR 0x60000000
32#define MMIO_RANGE_2_ADDR 0x70000000
33#define MMIO_RANGE_SIZE 0x200000
34
35/*
36 * Table of regions to map using the MMU.
37 */
38static const mmap_region_t tegra_mmap[] = {
Varun Wadekar08554a62017-06-12 16:47:16 -070039 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */
Varun Wadekara6a357f2017-05-05 09:20:59 -070040 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb316e242015-05-19 16:48:04 +053041 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
42 MT_DEVICE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
44 MT_DEVICE | MT_RW | MT_SECURE),
45 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
46 MT_DEVICE | MT_RW | MT_SECURE),
47 {0}
48};
49
50/*******************************************************************************
51 * Set up the pagetables as per the platform memory map & initialize the MMU
52 ******************************************************************************/
53const mmap_region_t *plat_get_mmio_map(void)
54{
Marvin Hsu21eea972017-04-11 11:00:48 +080055 /* Add the map region for security engine SE2 */
56 if (tegra_chipid_is_t210_b01()) {
57 mmap_add_region((uint64_t)TEGRA_SE2_BASE,
58 (uint64_t)TEGRA_SE2_BASE,
59 (uint64_t)TEGRA_SE2_RANGE_SIZE,
60 MT_DEVICE | MT_RW | MT_SECURE);
61 }
62
Varun Wadekarb316e242015-05-19 16:48:04 +053063 /* MMIO space */
64 return tegra_mmap;
65}
66
67/*******************************************************************************
Varun Wadekare34bc3d2017-04-28 08:43:33 -070068 * The Tegra power domain tree has a single system level power domain i.e. a
69 * single root node. The first entry in the power domain descriptor specifies
70 * the number of power domains at the highest power level.
71 *******************************************************************************
72 */
73const unsigned char tegra_power_domain_tree_desc[] = {
74 /* No of root nodes */
75 1,
76 /* No of clusters */
77 PLATFORM_CLUSTER_COUNT,
78 /* No of CPU cores - cluster0 */
79 PLATFORM_MAX_CPUS_PER_CLUSTER,
80 /* No of CPU cores - cluster1 */
81 PLATFORM_MAX_CPUS_PER_CLUSTER
82};
83
84/*******************************************************************************
85 * This function returns the Tegra default topology tree information.
86 ******************************************************************************/
87const unsigned char *plat_get_power_domain_tree_desc(void)
88{
89 return tegra_power_domain_tree_desc;
90}
91
92/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053093 * Handler to get the System Counter Frequency
94 ******************************************************************************/
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010095unsigned int plat_get_syscnt_freq2(void)
Varun Wadekarb316e242015-05-19 16:48:04 +053096{
97 return 19200000;
98}
Varun Wadekard2014c62015-10-29 10:37:28 +053099
100/*******************************************************************************
101 * Maximum supported UART controllers
102 ******************************************************************************/
103#define TEGRA210_MAX_UART_PORTS 5
104
105/*******************************************************************************
106 * This variable holds the UART port base addresses
107 ******************************************************************************/
108static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
109 0, /* undefined - treated as an error case */
110 TEGRA_UARTA_BASE,
111 TEGRA_UARTB_BASE,
112 TEGRA_UARTC_BASE,
113 TEGRA_UARTD_BASE,
114 TEGRA_UARTE_BASE,
115};
116
117/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700118 * Enable console corresponding to the console ID
Varun Wadekard2014c62015-10-29 10:37:28 +0530119 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700120void plat_enable_console(int32_t id)
Varun Wadekard2014c62015-10-29 10:37:28 +0530121{
Andre Przywara98b5a112020-01-25 00:58:35 +0000122 static console_t uart_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700123 uint32_t console_clock;
124
125 if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) {
126 /*
127 * Reference clock used by the FPGAs is a lot slower.
128 */
129 if (tegra_platform_is_fpga()) {
130 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
131 } else {
132 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
133 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530134
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700135 (void)console_16550_register(tegra210_uart_addresses[id],
136 console_clock,
137 TEGRA_CONSOLE_BAUDRATE,
138 &uart_console);
Andre Przywara98b5a112020-01-25 00:58:35 +0000139 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700140 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
141 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530142}
Varun Wadekarb7b45752015-12-28 14:55:41 -0800143
144/*******************************************************************************
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700145 * Return pointer to the BL31 params from previous bootloader
146 ******************************************************************************/
147struct tegra_bl31_params *plat_get_bl31_params(void)
148{
149 return NULL;
150}
151
152/*******************************************************************************
153 * Return pointer to the BL31 platform params from previous bootloader
154 ******************************************************************************/
155plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
156{
157 return NULL;
158}
159
160/*******************************************************************************
Marvin Hsu21eea972017-04-11 11:00:48 +0800161 * Handler for early platform setup
162 ******************************************************************************/
163void plat_early_platform_setup(void)
164{
Sam Payne71ce6ed2017-05-08 12:42:49 -0700165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
166 uint64_t val;
167
168 /* platform parameter passed by the previous bootloader */
169 if (plat_params->l2_ecc_parity_prot_dis != 1) {
170 /* Enable ECC Parity Protection for Cortex-A57 CPUs */
171 val = read_l2ctlr_el1();
172 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
173 write_l2ctlr_el1(val);
174 }
175
Marvin Hsu21eea972017-04-11 11:00:48 +0800176 /* Initialize security engine driver */
Harvey Hsieh1dbd19c2018-04-10 18:16:51 +0800177 tegra_se_init();
Marvin Hsu21eea972017-04-11 11:00:48 +0800178}
179
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800180/* Secure IRQs for Tegra186 */
181static const interrupt_prop_t tegra210_interrupt_props[] = {
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700182 INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekare7ff9cb2018-08-10 10:17:31 -0700183 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700184 INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800185 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
186};
187
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700188/*******************************************************************************
189 * Handler for late platform setup
190 ******************************************************************************/
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800191void plat_late_platform_setup(void)
192{
193 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800194 uint64_t sc7entry_end, offset;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800195 int ret;
Varun Wadekara8c61ac2018-03-12 15:11:55 -0700196 uint32_t val;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800197
198 /* memmap TZDRAM area containing the SC7 Entry Firmware */
199 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
200
Varun Wadekardae27962018-03-05 10:19:37 -0800201 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800202
203 /*
204 * Verify that the SC7 entry firmware resides inside the TZDRAM
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800205 * aperture, _before_ the BL31 code and the start address is
206 * exactly 1MB from BL31 base.
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800207 */
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800208
209 /* sc7entry-fw must be _before_ BL31 base */
210 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);
211
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800212 sc7entry_end = plat_params->sc7entry_fw_base +
213 plat_params->sc7entry_fw_size;
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800214 assert(sc7entry_end < plat_params->tzdram_base);
215
216 /* sc7entry-fw start must be exactly 1MB behind BL31 base */
217 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
218 assert(offset == 0x100000);
219
220 /* secure TZDRAM area */
221 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
222 plat_params->tzdram_size + offset);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800223
224 /* power off BPMP processor until SC7 entry */
225 tegra_fc_bpmp_off();
226
227 /* memmap SC7 entry firmware code */
228 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
229 plat_params->sc7entry_fw_base,
230 plat_params->sc7entry_fw_size,
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800231 MT_SECURE | MT_RO_DATA);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800232 assert(ret == 0);
Varun Wadekara8c61ac2018-03-12 15:11:55 -0700233
234 /* restrict PMC access to secure world */
235 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
236 val |= PMC_SECURITY_EN_BIT;
237 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800238 }
kalyani chidambaram52dc3ea2018-04-09 15:18:02 -0700239
240 if (!tegra_chipid_is_t210_b01()) {
241 /* restrict PMC access to secure world */
242 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
243 val |= PMC_SECURITY_EN_BIT;
244 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
245 }
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800246}
247
Marvin Hsu21eea972017-04-11 11:00:48 +0800248/*******************************************************************************
Varun Wadekarb7b45752015-12-28 14:55:41 -0800249 * Initialize the GIC and SGIs
250 ******************************************************************************/
251void plat_gic_setup(void)
252{
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800253 tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props));
Varun Wadekar84a775e2019-01-03 10:12:55 -0800254 tegra_gic_init();
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800255
256 /* Enable handling for FIQs */
257 tegra_fiq_handler_setup();
258
259 /*
260 * Enable routing watchdog FIQs from the flow controller to
261 * the GICD.
262 */
263 tegra_fc_enable_fiq_to_ccplex_routing();
Varun Wadekarb7b45752015-12-28 14:55:41 -0800264}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700265/*******************************************************************************
266 * Handler to indicate support for System Suspend
267 ******************************************************************************/
268bool plat_supports_system_suspend(void)
269{
270 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
271
272 /*
273 * sc7entry-fw is only supported by Tegra210 SoCs.
274 */
275 if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {
276 return true;
277 } else if (tegra_chipid_is_t210_b01()) {
278 return true;
279 } else {
280 return false;
281 }
282}