blob: a770255fc6dcb19b75bc2aa087476f10757eee67 [file] [log] [blame]
Aditya Angadiaaa7b272020-11-19 17:32:41 +05301/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <platform_def.h>
10
11#include <plat/arm/common/plat_arm.h>
12#include <plat/common/platform.h>
13#include <drivers/arm/sbsa.h>
14
15/*
16 * Table of regions for different BL stages to map using the MMU.
17 */
18#if IMAGE_BL1
19const mmap_region_t plat_arm_mmap[] = {
20 ARM_MAP_SHARED_RAM,
21 SGI_MAP_FLASH0_RO,
22 CSS_SGI_MAP_DEVICE,
23 SOC_PLATFORM_PERIPH_MAP_DEVICE,
24 SOC_SYSTEM_PERIPH_MAP_DEVICE,
25 {0}
26};
27#endif
28
29#if IMAGE_BL2
30const mmap_region_t plat_arm_mmap[] = {
31 ARM_MAP_SHARED_RAM,
32 SGI_MAP_FLASH0_RO,
33#ifdef PLAT_ARM_MEM_PROT_ADDR
34 ARM_V2M_MAP_MEM_PROTECT,
35#endif
36 CSS_SGI_MAP_DEVICE,
37 SOC_MEMCNTRL_MAP_DEVICE,
38 SOC_PLATFORM_PERIPH_MAP_DEVICE,
39 SOC_SYSTEM_PERIPH_MAP_DEVICE,
40 ARM_MAP_NS_DRAM1,
41#if ARM_BL31_IN_DRAM
42 ARM_MAP_BL31_SEC_DRAM,
43#endif
44#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
45 ARM_MAP_BL1_RW,
46#endif
47 {0}
48};
49#endif
50
51#if IMAGE_BL31
52const mmap_region_t plat_arm_mmap[] = {
53 ARM_MAP_SHARED_RAM,
54#ifdef PLAT_ARM_MEM_PROT_ADDR
55 ARM_V2M_MAP_MEM_PROTECT,
56#endif
57 CSS_SGI_MAP_DEVICE,
58 SOC_PLATFORM_PERIPH_MAP_DEVICE,
59 SOC_SYSTEM_PERIPH_MAP_DEVICE,
60 {0}
61};
62
63#endif
64
65ARM_CASSERT_MMAP
66
67#if TRUSTED_BOARD_BOOT
68int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
69{
70 assert(heap_addr != NULL);
71 assert(heap_size != NULL);
72
73 return arm_get_mbedtls_heap(heap_addr, heap_size);
74}
75#endif
76
77void plat_arm_secure_wdt_start(void)
78{
79 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
80}
81
82void plat_arm_secure_wdt_stop(void)
83{
84 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
85}