Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <bakery_lock.h> |
| 33 | #include <css_def.h> |
| 34 | #include <mmio.h> |
| 35 | #include <plat_arm.h> |
| 36 | #include "css_mhu.h" |
| 37 | |
| 38 | /* SCP MHU secure channel registers */ |
| 39 | #define SCP_INTR_S_STAT 0x200 |
| 40 | #define SCP_INTR_S_SET 0x208 |
| 41 | #define SCP_INTR_S_CLEAR 0x210 |
| 42 | |
| 43 | /* CPU MHU secure channel registers */ |
| 44 | #define CPU_INTR_S_STAT 0x300 |
| 45 | #define CPU_INTR_S_SET 0x308 |
| 46 | #define CPU_INTR_S_CLEAR 0x310 |
| 47 | |
| 48 | ARM_INSTANTIATE_LOCK |
| 49 | |
| 50 | /* Weak definition may be overridden in specific CSS based platform */ |
| 51 | #pragma weak plat_arm_pwrc_setup |
| 52 | |
| 53 | |
| 54 | void mhu_secure_message_start(void) |
| 55 | { |
| 56 | arm_lock_get(); |
| 57 | |
| 58 | /* Make sure any previous command has finished */ |
| 59 | while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0) |
| 60 | ; |
| 61 | } |
| 62 | |
| 63 | void mhu_secure_message_send(uint32_t command) |
| 64 | { |
| 65 | /* Send command to SCP and wait for it to pick it up */ |
| 66 | mmio_write_32(MHU_BASE + CPU_INTR_S_SET, command); |
| 67 | while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0) |
| 68 | ; |
| 69 | } |
| 70 | |
| 71 | uint32_t mhu_secure_message_wait(void) |
| 72 | { |
| 73 | /* Wait for response from SCP */ |
| 74 | uint32_t response; |
| 75 | while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT))) |
| 76 | ; |
| 77 | |
| 78 | return response; |
| 79 | } |
| 80 | |
| 81 | void mhu_secure_message_end(void) |
| 82 | { |
| 83 | /* |
| 84 | * Clear any response we got by writing all ones to the CLEAR |
| 85 | * register |
| 86 | */ |
| 87 | mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 0xffffffffu); |
| 88 | |
| 89 | arm_lock_release(); |
| 90 | } |
| 91 | |
| 92 | void mhu_secure_init(void) |
| 93 | { |
| 94 | arm_lock_init(); |
| 95 | |
| 96 | /* |
| 97 | * Clear the CPU's INTR register to make sure we don't see a stale |
| 98 | * or garbage value and think it's a message we've already sent. |
| 99 | */ |
| 100 | mmio_write_32(MHU_BASE + CPU_INTR_S_CLEAR, 0xffffffffu); |
| 101 | } |
| 102 | |
| 103 | void plat_arm_pwrc_setup(void) |
| 104 | { |
| 105 | mhu_secure_init(); |
| 106 | } |