blob: 9728a0874e8c36f5ee5fbe68681833c6ad4dad60 [file] [log] [blame]
Pranav Madhu078dc522022-07-27 14:01:24 +05301# Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
Aditya Angadid61740b2020-11-19 18:05:33 +05302#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
Aditya Angadiccae8a12021-08-09 09:38:58 +05306RD_N2_VARIANTS := 0 1 2
7ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
8 $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
9 $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1 or 2, currently set \
10 to ${CSS_SGI_PLATFORM_VARIANT}.")
11endif
12
13$(eval $(call CREATE_SEQ,SEQ,4))
14ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
15 $(error "Chip count for RD-N2-MC should be either $(SEQ) \
16 currently it is set to ${CSS_SGI_CHIP_COUNT}.")
17endif
18
Andre Przywarab6c24ce2021-07-20 19:20:07 +010019# RD-N2 platform uses GIC-700 which is based on GICv4.1
Aditya Angadid61740b2020-11-19 18:05:33 +053020GIC_ENABLE_V4_EXTN := 1
21
Aditya Angadiccae8a12021-08-09 09:38:58 +053022#Enable GIC Multichip Extension only for Multichip Platforms
23ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
24GICV3_IMPL_GIC600_MULTICHIP := 1
25endif
26
Pranav Madhu078dc522022-07-27 14:01:24 +053027override CSS_SYSTEM_GRACEFUL_RESET := 1
28override EL3_EXCEPTION_HANDLING := 1
29
Aditya Angadid61740b2020-11-19 18:05:33 +053030include plat/arm/css/sgi/sgi-common.mk
31
32RDN2_BASE = plat/arm/board/rdn2
33
34PLAT_INCLUDES += -I${RDN2_BASE}/include/
35
Tony K Nadackale23ca812021-08-19 14:44:11 +010036SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
Joel Goddarda1c50ab2022-09-21 21:52:28 +053037 lib/cpus/aarch64/neoverse_v2.S
Aditya Angadid61740b2020-11-19 18:05:33 +053038
39PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c
40
41BL1_SOURCES += ${SGI_CPU_SOURCES} \
42 ${RDN2_BASE}/rdn2_err.c
43
44BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
45 ${RDN2_BASE}/rdn2_security.c \
46 ${RDN2_BASE}/rdn2_err.c \
47 lib/utils/mem_region.c \
48 drivers/arm/tzc/tzc400.c \
49 plat/arm/common/arm_tzc400.c \
50 plat/arm/common/arm_nor_psci_mem_protect.c
51
52BL31_SOURCES += ${SGI_CPU_SOURCES} \
53 ${RDN2_BASE}/rdn2_plat.c \
54 ${RDN2_BASE}/rdn2_topology.c \
55 drivers/cfi/v2m/v2m_flash.c \
56 lib/utils/mem_region.c \
57 plat/arm/common/arm_nor_psci_mem_protect.c
58
59ifeq (${TRUSTED_BOARD_BOOT}, 1)
60BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
61BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
62endif
63
Aditya Angadiccae8a12021-08-09 09:38:58 +053064ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
65BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
66
67# Enable dynamic addition of MMAP regions in BL31
68BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
69endif
70
Aditya Angadid61740b2020-11-19 18:05:33 +053071# Add the FDT_SOURCES and options for Dynamic Config
72FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
73 ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
74FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
75TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
76
77# Add the FW_CONFIG to FIP and specify the same to certtool
78$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
79# Add the TB_FW_CONFIG to FIP and specify the same to certtool
80$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
81
82FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts
83NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
84
85# Add the NT_FW_CONFIG to FIP and specify the same to certtool
86$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
87
88override CTX_INCLUDE_AARCH32_REGS := 0
Pranav Madhu40ebb322021-01-27 16:17:32 +053089override ENABLE_AMU := 1