Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 1 | /* |
Samuel Holland | d00eaa2 | 2019-10-27 14:07:52 -0500 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/tbbr/tbbr_img_def.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | #include <plat/common/common_def.h> |
| 13 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 14 | #include <sunxi_mmap.h> |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 15 | |
Samuel Holland | 38d98de | 2019-02-17 15:10:36 -0600 | [diff] [blame] | 16 | #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) |
Samuel Holland | d002f3b | 2019-12-29 12:22:55 -0600 | [diff] [blame] | 17 | #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ |
| 18 | SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) |
| 19 | |
| 20 | /* The SCP firmware is allocated the last 16KiB of SRAM A2. */ |
| 21 | #define SUNXI_SCP_BASE BL31_LIMIT |
| 22 | #define SUNXI_SCP_SIZE 0x4000 |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 23 | |
Samuel Holland | d00eaa2 | 2019-10-27 14:07:52 -0500 | [diff] [blame] | 24 | /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ |
| 25 | #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) |
| 26 | #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) |
| 27 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 28 | /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ |
| 29 | #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) |
| 30 | |
Andre Przywara | b3fddff | 2018-09-20 21:13:55 +0100 | [diff] [blame] | 31 | /* How much memory to reserve as secure for BL32, if configured */ |
| 32 | #define SUNXI_DRAM_SEC_SIZE (32U << 20) |
| 33 | |
Andre Przywara | ea5fa47 | 2018-09-16 02:08:06 +0100 | [diff] [blame] | 34 | /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ |
Andre Przywara | b3fddff | 2018-09-20 21:13:55 +0100 | [diff] [blame] | 35 | #define SUNXI_DRAM_MAP_SIZE (64U << 20) |
| 36 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 37 | #define CACHE_WRITEBACK_SHIFT 6 |
| 38 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 39 | |
Samuel Holland | a4fbdfa | 2019-10-27 17:30:15 -0500 | [diff] [blame] | 40 | #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) |
Andre Przywara | b3fddff | 2018-09-20 21:13:55 +0100 | [diff] [blame] | 41 | #define MAX_XLAT_TABLES 1 |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 42 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 43 | #define PLAT_MAX_PWR_LVL_STATES U(2) |
| 44 | #define PLAT_MAX_RET_STATE U(1) |
| 45 | #define PLAT_MAX_OFF_STATE U(2) |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 46 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 47 | #define PLAT_MAX_PWR_LVL U(2) |
Deepika Bhavnani | fa4e1d0 | 2019-12-13 10:48:27 -0600 | [diff] [blame] | 48 | #define PLAT_NUM_PWR_DOMAINS (U(1) + \ |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 49 | PLATFORM_CLUSTER_COUNT + \ |
| 50 | PLATFORM_CORE_COUNT) |
| 51 | |
| 52 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
Andre Przywara | b3fddff | 2018-09-20 21:13:55 +0100 | [diff] [blame] | 53 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 54 | |
Deepika Bhavnani | fa4e1d0 | 2019-12-13 10:48:27 -0600 | [diff] [blame] | 55 | #define PLATFORM_CLUSTER_COUNT U(1) |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 56 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ |
| 57 | PLATFORM_MAX_CPUS_PER_CLUSTER) |
Deepika Bhavnani | fa4e1d0 | 2019-12-13 10:48:27 -0600 | [diff] [blame] | 58 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) |
Samuel Holland | d002f3b | 2019-12-29 12:22:55 -0600 | [diff] [blame] | 59 | #define PLATFORM_MMAP_REGIONS 5 |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 60 | #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) |
| 61 | |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 62 | #ifndef SPD_none |
| 63 | #ifndef BL32_BASE |
| 64 | #define BL32_BASE SUNXI_DRAM_BASE |
| 65 | #endif |
| 66 | #endif |
| 67 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 68 | #endif /* PLATFORM_DEF_H */ |