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developer1033ea12019-04-10 21:09:26 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MT8183_MCUCFG_H
8#define MT8183_MCUCFG_H
9
10#include <platform_def.h>
11#include <stdint.h>
12
13struct mt8183_mcucfg_regs {
14 uint32_t mp0_ca7l_cache_config; /* 0x0 */
15 struct {
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
18 } mp0_cpu[4]; /* 0x4 */
19 uint32_t mp0_cache_mem_delsel0; /* 0x24 */
20 uint32_t mp0_cache_mem_delsel1; /* 0x28 */
21 uint32_t mp0_axi_config; /* 0x2C */
22 uint32_t mp0_misc_config[10]; /* 0x30 */
23 uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
24 uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
25 uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
26 uint32_t mp0_ca7l_misc_config; /* 0x64 */
27 uint32_t mp0_ca7l_dbg_pwr_ctrl; /* 0x68 */
28 uint32_t mp0_rw_rsvd0; /* 0x6C */
29 uint32_t mp0_rw_rsvd1; /* 0x70 */
30 uint32_t mp0_ro_rsvd; /* 0x74 */
31 uint32_t reserved0_0[98]; /* 0x78 */
32 uint32_t mp1_ca7l_cache_config; /* 0x200 */
33 uint32_t mp1_miscdbg; /* 0x204 */
34 uint32_t reserved0_1[9]; /* 0x208 */
35 uint32_t mp1_axi_config; /* 0x22C */
36 uint32_t mp1_misc_config[10]; /* 0x230 */
37 uint32_t reserved0_2[3]; /* 0x258 */
38 uint32_t mp1_ca7l_misc_config; /* 0x264 */
39 uint32_t reserved0_3[310]; /* 0x268 */
40 uint32_t cci_adb400_dcm_config; /* 0x740 */
41 uint32_t sync_dcm_config; /* 0x744 */
42 uint32_t reserved0_4[16]; /* 0x748 */
43 uint32_t mp0_cputop_spmc_ctl; /* 0x788 */
44 uint32_t mp1_cputop_spmc_ctl; /* 0x78C */
45 uint32_t mp1_cputop_spmc_sram_ctl; /* 0x790 */
46 uint32_t reserved0_5[23]; /* 0x794 */
47 uint32_t l2_cfg_mp0; /* 0x7F0 */
48 uint32_t l2_cfg_mp1; /* 0x7F4 */
49 uint32_t reserved0_6[1282]; /* 0x7F8 */
50 uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */
51 uint32_t cpusys0_sparken; /* 0x1C04 */
52 uint32_t cpusys0_amuxsel; /* 0x1C08 */
53 uint32_t reserved0_7[9]; /* 0x1C0C */
54 uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */
55 uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */
56 uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */
57 uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */
58 uint32_t reserved0_8[370]; /* 0x1C40 */
59 uint32_t mp2_cpucfg; /* 0x2208 */
60 uint32_t mp2_axi_config; /* 0x220C */
61 uint32_t reserved0_9[36]; /* 0x2210 */
62 uint32_t mp2_cputop_spm_ctl; /* 0x22A0 */
63 uint32_t mp2_cputop_spm_sta; /* 0x22A4 */
64 uint32_t reserved0_10[98]; /* 0x22A8 */
65 uint32_t cpusys2_cpu0_spmc_ctl; /* 0x2430 */
66 uint32_t cpusys2_cpu0_spmc_sta; /* 0x2434 */
67 uint32_t cpusys2_cpu1_spmc_ctl; /* 0x2438 */
68 uint32_t cpusys2_cpu1_spmc_sta; /* 0x243C */
69 uint32_t reserved0_11[176]; /* 0x2440 */
70 uint32_t spark2ld0; /* 0x2700 */
71 uint32_t reserved0_12[1355]; /* 0x2704 */
72 uint32_t cpusys1_cpu0_spmc_ctl; /* 0x3C30 */
73 uint32_t cpusys1_cpu1_spmc_ctl; /* 0x3C34 */
74 uint32_t cpusys1_cpu2_spmc_ctl; /* 0x3C38 */
75 uint32_t cpusys1_cpu3_spmc_ctl; /* 0x3C3C */
76};
77
78static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
79
80enum {
81 SW_SPARK_EN = 1 << 0,
82 SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
83 SW_FSM_OVERRIDE = 1 << 2,
84 SW_LOGIC_PRE1_PDB = 1 << 3,
85 SW_LOGIC_PRE2_PDB = 1 << 4,
86 SW_LOGIC_PDB = 1 << 5,
87 SW_ISO = 1 << 6,
88 SW_SRAM_SLEEPB = 0x3f << 7,
89 SW_SRAM_ISOINTB = 1 << 13,
90 SW_CLK_DIS = 1 << 14,
91 SW_CKISO = 1 << 15,
92 SW_PD = 0x3f << 16,
93 SW_HOT_PLUG_RESET = 1 << 22,
94 SW_PWR_ON_OVERRIDE_EN = 1 << 23,
95 SW_PWR_ON = 1 << 24,
96 SW_COQ_DIS = 1 << 25,
97 LOGIC_PDBO_ALL_OFF_ACK = 1 << 26,
98 LOGIC_PDBO_ALL_ON_ACK = 1 << 27,
99 LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 28,
100 LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 29
101};
102
103enum {
104 CPU_SW_SPARK_EN = 1 << 0,
105 CPU_SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
106 CPU_SW_FSM_OVERRIDE = 1 << 2,
107 CPU_SW_LOGIC_PRE1_PDB = 1 << 3,
108 CPU_SW_LOGIC_PRE2_PDB = 1 << 4,
109 CPU_SW_LOGIC_PDB = 1 << 5,
110 CPU_SW_ISO = 1 << 6,
111 CPU_SW_SRAM_SLEEPB = 1 << 7,
112 CPU_SW_SRAM_ISOINTB = 1 << 8,
113 CPU_SW_CLK_DIS = 1 << 9,
114 CPU_SW_CKISO = 1 << 10,
115 CPU_SW_PD = 0x1f << 11,
116 CPU_SW_HOT_PLUG_RESET = 1 << 16,
117 CPU_SW_POWR_ON_OVERRIDE_EN = 1 << 17,
118 CPU_SW_PWR_ON = 1 << 18,
119 CPU_SPARK2LDO_ALLSWOFF = 1 << 19,
120 CPU_PDBO_ALL_ON_ACK = 1 << 20,
121 CPU_PRE2_PDBO_ALLON_ACK = 1 << 21,
122 CPU_PRE1_PDBO_ALLON_ACK = 1 << 22
123};
124
125enum {
126 MP2_AXI_CONFIG_ACINACTM = 1 << 0,
127 MPx_AXI_CONFIG_ACINACTM = 1 << 4,
128 MPX_CA7_MISC_CONFIG_STANDBYWFIL2 = 1 << 28
129};
130
131enum {
132 MP0_CPU0_STANDBYWFE = 1 << 20,
133 MP0_CPU1_STANDBYWFE = 1 << 21,
134 MP0_CPU2_STANDBYWFE = 1 << 22,
135 MP0_CPU3_STANDBYWFE = 1 << 23
136};
137
138enum {
139 MP1_CPU0_STANDBYWFE = 1 << 20,
140 MP1_CPU1_STANDBYWFE = 1 << 21,
141 MP1_CPU2_STANDBYWFE = 1 << 22,
142 MP1_CPU3_STANDBYWFE = 1 << 23
143};
144
145enum {
146 B_SW_HOT_PLUG_RESET = 1 << 30,
147 B_SW_PD_OFFSET = 18,
148 B_SW_PD = 0x3f << B_SW_PD_OFFSET,
149 B_SW_SRAM_SLEEPB_OFFSET = 12,
150 B_SW_SRAM_SLEEPB = 0x3f << B_SW_SRAM_SLEEPB_OFFSET
151};
152
153enum {
154 B_SW_SRAM_ISOINTB = 1 << 9,
155 B_SW_ISO = 1 << 8,
156 B_SW_LOGIC_PDB = 1 << 7,
157 B_SW_LOGIC_PRE2_PDB = 1 << 6,
158 B_SW_LOGIC_PRE1_PDB = 1 << 5,
159 B_SW_FSM_OVERRIDE = 1 << 4,
160 B_SW_PWR_ON = 1 << 3,
161 B_SW_PWR_ON_OVERRIDE_EN = 1 << 2
162};
163
164enum {
165 B_FSM_STATE_OUT_OFFSET = 6,
166 B_FSM_STATE_OUT_MASK = 0x1f << B_FSM_STATE_OUT_OFFSET,
167 B_SW_LOGIC_PDBO_ALL_OFF_ACK = 1 << 5,
168 B_SW_LOGIC_PDBO_ALL_ON_ACK = 1 << 4,
169 B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 3,
170 B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 2,
171 B_FSM_OFF = 0 << B_FSM_STATE_OUT_OFFSET,
172 B_FSM_ON = 1 << B_FSM_STATE_OUT_OFFSET,
173 B_FSM_RET = 2 << B_FSM_STATE_OUT_OFFSET
174};
175
176/* APB Module infracfg_ao */
177enum {
178 INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250,
179 INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258,
180 INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8,
181 INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC
182};
183
184enum {
185 IDX_PROTECT_MP0_CACTIVE = 10,
186 IDX_PROTECT_MP1_CACTIVE = 11,
187 IDX_PROTECT_ICC0_CACTIVE = 12,
188 IDX_PROTECT_ICD0_CACTIVE = 13,
189 IDX_PROTECT_ICC1_CACTIVE = 14,
190 IDX_PROTECT_ICD1_CACTIVE = 15,
191 IDX_PROTECT_L2C0_CACTIVE = 26,
192 IDX_PROTECT_L2C1_CACTIVE = 27
193};
194
195/* cpu boot mode */
196enum {
197 MP0_CPUCFG_64BIT_SHIFT = 12,
198 MP1_CPUCFG_64BIT_SHIFT = 28,
199 MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
200 MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
201};
202
203/* scu related */
204enum {
205 MP0_ACINACTM_SHIFT = 4,
206 MP1_ACINACTM_SHIFT = 4,
207 MP2_ACINACTM_SHIFT = 0,
208 MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
209 MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT,
210 MP2_ACINACTM = 1 << MP2_ACINACTM_SHIFT
211};
212
213enum {
214 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
215 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
216 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
217 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
218 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
219
220 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
221 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
222 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
223 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
224 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
225 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
226 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
227 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
228 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
229 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
230};
231
232enum {
233 MP1_AINACTS_SHIFT = 4,
234 MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
235};
236
237enum {
238 MP1_SW_CG_GEN_SHIFT = 12,
239 MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
240};
241
242enum {
243 MP1_L2RSTDISABLE_SHIFT = 14,
244 MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
245};
246
247#endif /* MT8183_MCUCFG_H */