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git01.mediatek.com / filogic / atf / 1017a6ec6bc0498f5b32f4946839043b70c4cc8c / . / plat / qemu / qemu_bl2_mem_params_desc.c
blob: 3396140a13536ce2f82d49970a703a65bb5650e4 [file] [log] [blame]
Fu Weic2f78442017-05-27 21:21:42 +0800[diff] [blame]1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <desc_image_load.h>
8#include <platform.h>
9#include <platform_def.h>
10
11/*******************************************************************************
12 * Following descriptor provides BL image/ep information that gets used
13 * by BL2 to load the images and also subset of this information is
14 * passed to next BL image. The image loading sequence is managed by
15 * populating the images in required loading order. The image execution
16 * sequence is managed by populating the `next_handoff_image_id` with
17 * the next executable image id.
18 ******************************************************************************/
19static bl_mem_params_node_t bl2_mem_params_descs[] = {
20#ifdef EL3_PAYLOAD_BASE
21 /* Fill EL3 payload related information (BL31 is EL3 payload) */
22 { .image_id = BL31_IMAGE_ID,
23
24 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
25 entry_point_info_t,
26 SECURE | EXECUTABLE | EP_FIRST_EXE),
27 .ep_info.pc = EL3_PAYLOAD_BASE,
28 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
29 DISABLE_ALL_EXCEPTIONS),
30
31 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
32 IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
33
34 .next_handoff_image_id = INVALID_IMAGE_ID,
35 },
36#else /* EL3_PAYLOAD_BASE */
37 /* Fill BL31 related information */
38 { .image_id = BL31_IMAGE_ID,
39
40 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
41 entry_point_info_t,
42 SECURE | EXECUTABLE | EP_FIRST_EXE),
43 .ep_info.pc = BL31_BASE,
44 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
45 DISABLE_ALL_EXCEPTIONS),
46# if DEBUG
47 .ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL,
48# endif
49 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
50 IMAGE_ATTRIB_PLAT_SETUP),
51 .image_info.image_base = BL31_BASE,
52 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
53
54# ifdef QEMU_LOAD_BL32
55 .next_handoff_image_id = BL32_IMAGE_ID,
56# else
57 .next_handoff_image_id = BL33_IMAGE_ID,
58# endif
59 },
60# ifdef QEMU_LOAD_BL32
61 /* Fill BL32 related information */
62 { .image_id = BL32_IMAGE_ID,
63
64 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
65 entry_point_info_t, SECURE | EXECUTABLE),
66 .ep_info.pc = BL32_BASE,
67
68 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
69 0),
70 .image_info.image_base = BL32_BASE,
71 .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
72
73 .next_handoff_image_id = BL33_IMAGE_ID,
74 },
75# endif /* QEMU_LOAD_BL32 */
76
77 /* Fill BL33 related information */
78 { .image_id = BL33_IMAGE_ID,
79 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
80 entry_point_info_t, NON_SECURE | EXECUTABLE),
81# ifdef PRELOADED_BL33_BASE
82 .ep_info.pc = PRELOADED_BL33_BASE,
83
84 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
85 IMAGE_ATTRIB_SKIP_LOADING),
86# else /* PRELOADED_BL33_BASE */
87 .ep_info.pc = NS_IMAGE_OFFSET,
88
89 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
90 0),
91 .image_info.image_base = NS_IMAGE_OFFSET,
92 .image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE -
93 NS_IMAGE_OFFSET,
94# endif /* !PRELOADED_BL33_BASE */
95
96 .next_handoff_image_id = INVALID_IMAGE_ID,
97 }
98#endif /* !EL3_PAYLOAD_BASE */
99};
100
101REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)