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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Roberto Vargas0fccc502018-04-23 14:44:54 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
Achin Gupta69387312016-09-26 10:22:56 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7 motherboard {
8 arm,v2m-memory-map = "rs1";
9 compatible = "arm,vexpress,v2m-p1", "simple-bus";
10 #address-cells = <2>; /* SMB chipselect number and offset */
11 #size-cells = <1>;
Achin Gupta4f6ad662013-10-25 09:08:21 +010012 ranges;
13
14 flash@0,00000000 {
15 compatible = "arm,vexpress-flash", "cfi-flash";
16 reg = <0 0x00000000 0x04000000>,
17 <4 0x00000000 0x04000000>;
18 bank-width = <4>;
19 };
20
21 vram@2,00000000 {
22 compatible = "arm,vexpress-vram";
23 reg = <2 0x00000000 0x00800000>;
24 };
25
26 ethernet@2,02000000 {
27 compatible = "smsc,lan91c111";
28 reg = <2 0x02000000 0x10000>;
Achin Gupta69387312016-09-26 10:22:56 +010029 interrupts = <0 15 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +010030 };
31
32 v2m_clk24mhz: clk24mhz {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <24000000>;
36 clock-output-names = "v2m:clk24mhz";
37 };
38
39 v2m_refclk1mhz: refclk1mhz {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <1000000>;
43 clock-output-names = "v2m:refclk1mhz";
44 };
45
46 v2m_refclk32khz: refclk32khz {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <32768>;
50 clock-output-names = "v2m:refclk32khz";
51 };
52
53 iofpga@3,00000000 {
54 compatible = "arm,amba-bus", "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges = <0 3 0 0x200000>;
58
Roberto Vargas0fccc502018-04-23 14:44:54 +010059 v2m_sysreg: sysreg@10000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +010060 compatible = "arm,vexpress-sysreg";
61 reg = <0x010000 0x1000>;
62 gpio-controller;
63 #gpio-cells = <2>;
64 };
65
Roberto Vargas0fccc502018-04-23 14:44:54 +010066 v2m_sysctl: sysctl@20000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 compatible = "arm,sp810", "arm,primecell";
68 reg = <0x020000 0x1000>;
69 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
70 clock-names = "refclk", "timclk", "apb_pclk";
71 #clock-cells = <1>;
72 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
73 };
74
Roberto Vargas0fccc502018-04-23 14:44:54 +010075 aaci@40000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +010076 compatible = "arm,pl041", "arm,primecell";
77 reg = <0x040000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +010078 interrupts = <0 11 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +010079 clocks = <&v2m_clk24mhz>;
80 clock-names = "apb_pclk";
81 };
82
Roberto Vargas0fccc502018-04-23 14:44:54 +010083 mmci@50000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +010084 compatible = "arm,pl180", "arm,primecell";
85 reg = <0x050000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +010086 interrupts = <0 9 4 0 10 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +010087 cd-gpios = <&v2m_sysreg 0 0>;
88 wp-gpios = <&v2m_sysreg 1 0>;
89 max-frequency = <12000000>;
90 vmmc-supply = <&v2m_fixed_3v3>;
91 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
92 clock-names = "mclk", "apb_pclk";
93 };
94
Roberto Vargas0fccc502018-04-23 14:44:54 +010095 kmi@60000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +010096 compatible = "arm,pl050", "arm,primecell";
97 reg = <0x060000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +010098 interrupts = <0 12 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
100 clock-names = "KMIREFCLK", "apb_pclk";
101 };
102
Roberto Vargas0fccc502018-04-23 14:44:54 +0100103 kmi@70000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 compatible = "arm,pl050", "arm,primecell";
105 reg = <0x070000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100106 interrupts = <0 13 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
108 clock-names = "KMIREFCLK", "apb_pclk";
109 };
110
Roberto Vargas0fccc502018-04-23 14:44:54 +0100111 v2m_serial0: uart@90000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112 compatible = "arm,pl011", "arm,primecell";
113 reg = <0x090000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100114 interrupts = <0 5 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
116 clock-names = "uartclk", "apb_pclk";
117 };
118
Roberto Vargas0fccc502018-04-23 14:44:54 +0100119 v2m_serial1: uart@a0000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120 compatible = "arm,pl011", "arm,primecell";
121 reg = <0x0a0000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100122 interrupts = <0 6 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
124 clock-names = "uartclk", "apb_pclk";
125 };
126
Roberto Vargas0fccc502018-04-23 14:44:54 +0100127 v2m_serial2: uart@b0000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0b0000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100130 interrupts = <0 7 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100131 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
132 clock-names = "uartclk", "apb_pclk";
133 };
134
Roberto Vargas0fccc502018-04-23 14:44:54 +0100135 v2m_serial3: uart@c0000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 compatible = "arm,pl011", "arm,primecell";
137 reg = <0x0c0000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100138 interrupts = <0 8 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
140 clock-names = "uartclk", "apb_pclk";
141 };
142
Roberto Vargas0fccc502018-04-23 14:44:54 +0100143 wdt@f0000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144 compatible = "arm,sp805", "arm,primecell";
145 reg = <0x0f0000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100146 interrupts = <0 0 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
148 clock-names = "wdogclk", "apb_pclk";
149 };
150
151 v2m_timer01: timer@110000 {
152 compatible = "arm,sp804", "arm,primecell";
153 reg = <0x110000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100154 interrupts = <0 2 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100155 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
156 clock-names = "timclken1", "timclken2", "apb_pclk";
157 };
158
159 v2m_timer23: timer@120000 {
160 compatible = "arm,sp804", "arm,primecell";
161 reg = <0x120000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100162 interrupts = <0 3 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
164 clock-names = "timclken1", "timclken2", "apb_pclk";
165 };
166
167 rtc@170000 {
168 compatible = "arm,pl031", "arm,primecell";
169 reg = <0x170000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100170 interrupts = <0 4 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171 clocks = <&v2m_clk24mhz>;
172 clock-names = "apb_pclk";
173 };
174
175 clcd@1f0000 {
176 compatible = "arm,pl111", "arm,primecell";
177 reg = <0x1f0000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100178 interrupts = <0 14 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
180 clock-names = "clcdclk", "apb_pclk";
181 mode = "XVGA";
182 use_dma = <0>;
183 framebuffer = <0x18000000 0x00180000>;
184 };
185
Roberto Vargas0fccc502018-04-23 14:44:54 +0100186 virtio_block@130000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187 compatible = "virtio,mmio";
188 reg = <0x130000 0x1000>;
Achin Gupta69387312016-09-26 10:22:56 +0100189 interrupts = <0 0x2a 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190 };
191 };
192
Roberto Vargas0fccc502018-04-23 14:44:54 +0100193 v2m_fixed_3v3: fixedregulator {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194 compatible = "regulator-fixed";
195 regulator-name = "3V3";
196 regulator-min-microvolt = <3300000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-always-on;
199 };
200
201 mcc {
202 compatible = "arm,vexpress,config-bus", "simple-bus";
203 arm,vexpress,config-bridge = <&v2m_sysreg>;
204
Roberto Vargas0fccc502018-04-23 14:44:54 +0100205 v2m_oscclk1: osc {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206 /* CLCD clock */
207 compatible = "arm,vexpress-osc";
208 arm,vexpress-sysreg,func = <1 1>;
209 freq-range = <23750000 63500000>;
210 #clock-cells = <0>;
211 clock-output-names = "v2m:oscclk1";
212 };
213
Juan Castillo4dc4a472014-08-12 11:17:06 +0100214 /*
215 * Not supported in FVP models
216 *
217 * reset@0 {
218 * compatible = "arm,vexpress-reset";
219 * arm,vexpress-sysreg,func = <5 0>;
220 * };
221 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222
Roberto Vargas0fccc502018-04-23 14:44:54 +0100223 muxfpga {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224 compatible = "arm,vexpress-muxfpga";
225 arm,vexpress-sysreg,func = <7 0>;
226 };
227
Juan Castillo4dc4a472014-08-12 11:17:06 +0100228 /*
229 * Not used - Superseded by PSCI sys_poweroff
230 *
231 * shutdown@0 {
232 * compatible = "arm,vexpress-shutdown";
233 * arm,vexpress-sysreg,func = <8 0>;
234 * };
235 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236
Juan Castillo4dc4a472014-08-12 11:17:06 +0100237 /*
238 * Not used - Superseded by PSCI sys_reset
239 *
240 * reboot@0 {
241 * compatible = "arm,vexpress-reboot";
242 * arm,vexpress-sysreg,func = <9 0>;
243 * };
244 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100245
Roberto Vargas0fccc502018-04-23 14:44:54 +0100246 dvimode {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247 compatible = "arm,vexpress-dvimode";
248 arm,vexpress-sysreg,func = <11 0>;
249 };
250 };
251 };