Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __GICV3_H__ |
| 32 | #define __GICV3_H__ |
| 33 | |
| 34 | /******************************************************************************* |
| 35 | * GICv3 miscellaneous definitions |
| 36 | ******************************************************************************/ |
| 37 | /* Interrupt group definitions */ |
Soby Mathew | 5c5c36b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 38 | #define INTR_GROUP1S 0 |
| 39 | #define INTR_GROUP0 1 |
| 40 | #define INTR_GROUP1NS 2 |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 41 | |
| 42 | /* Interrupt IDs reported by the HPPIR and IAR registers */ |
| 43 | #define PENDING_G1S_INTID 1020 |
| 44 | #define PENDING_G1NS_INTID 1021 |
| 45 | |
| 46 | /* Constant to categorize LPI interrupt */ |
| 47 | #define MIN_LPI_ID 8192 |
| 48 | |
| 49 | /******************************************************************************* |
| 50 | * GICv3 specific Distributor interface register offsets and constants. |
| 51 | ******************************************************************************/ |
| 52 | #define GICD_STATUSR 0x10 |
| 53 | #define GICD_SETSPI_NSR 0x40 |
| 54 | #define GICD_CLRSPI_NSR 0x48 |
| 55 | #define GICD_SETSPI_SR 0x50 |
| 56 | #define GICD_CLRSPI_SR 0x50 |
| 57 | #define GICD_IGRPMODR 0xd00 |
| 58 | #define GICD_IROUTER 0x6100 |
| 59 | #define GICD_PIDR2_GICV3 0xffe8 |
| 60 | |
| 61 | #define IGRPMODR_SHIFT 5 |
| 62 | |
| 63 | /* GICD_CTLR bit definitions */ |
| 64 | #define CTLR_ENABLE_G1NS_SHIFT 1 |
| 65 | #define CTLR_ENABLE_G1S_SHIFT 2 |
| 66 | #define CTLR_ARE_S_SHIFT 4 |
| 67 | #define CTLR_ARE_NS_SHIFT 5 |
| 68 | #define CTLR_DS_SHIFT 6 |
| 69 | #define CTLR_E1NWF_SHIFT 7 |
| 70 | #define GICD_CTLR_RWP_SHIFT 31 |
| 71 | |
| 72 | #define CTLR_ENABLE_G1NS_MASK 0x1 |
| 73 | #define CTLR_ENABLE_G1S_MASK 0x1 |
| 74 | #define CTLR_ARE_S_MASK 0x1 |
| 75 | #define CTLR_ARE_NS_MASK 0x1 |
| 76 | #define CTLR_DS_MASK 0x1 |
| 77 | #define CTLR_E1NWF_MASK 0x1 |
| 78 | #define GICD_CTLR_RWP_MASK 0x1 |
| 79 | |
| 80 | #define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) |
| 81 | #define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) |
| 82 | #define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) |
| 83 | #define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) |
| 84 | #define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) |
| 85 | #define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) |
| 86 | #define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) |
| 87 | |
| 88 | /* GICD_IROUTER shifts and masks */ |
| 89 | #define IROUTER_IRM_SHIFT 31 |
| 90 | #define IROUTER_IRM_MASK 0x1 |
| 91 | |
| 92 | /******************************************************************************* |
| 93 | * GICv3 Re-distributor interface registers & constants |
| 94 | ******************************************************************************/ |
| 95 | #define GICR_PCPUBASE_SHIFT 0x11 |
| 96 | #define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ |
| 97 | #define GICR_CTLR 0x0 |
| 98 | #define GICR_TYPER 0x08 |
| 99 | #define GICR_WAKER 0x14 |
| 100 | #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) |
| 101 | #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) |
| 102 | #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) |
| 103 | #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) |
| 104 | #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) |
| 105 | #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) |
| 106 | #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) |
| 107 | |
| 108 | /* GICR_CTLR bit definitions */ |
| 109 | #define GICR_CTLR_RWP_SHIFT 3 |
| 110 | #define GICR_CTLR_RWP_MASK 0x1 |
| 111 | #define GICR_CTLR_RWP_BIT (1 << GICR_CTLR_RWP_SHIFT) |
| 112 | |
| 113 | /* GICR_WAKER bit definitions */ |
| 114 | #define WAKER_CA_SHIFT 2 |
| 115 | #define WAKER_PS_SHIFT 1 |
| 116 | |
| 117 | #define WAKER_CA_MASK 0x1 |
| 118 | #define WAKER_PS_MASK 0x1 |
| 119 | |
| 120 | #define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) |
| 121 | #define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) |
| 122 | |
| 123 | /* GICR_TYPER bit definitions */ |
| 124 | #define TYPER_AFF_VAL_SHIFT 32 |
| 125 | #define TYPER_PROC_NUM_SHIFT 8 |
| 126 | #define TYPER_LAST_SHIFT 4 |
| 127 | |
| 128 | #define TYPER_AFF_VAL_MASK 0xffffffff |
| 129 | #define TYPER_PROC_NUM_MASK 0xffff |
| 130 | #define TYPER_LAST_MASK 0x1 |
| 131 | |
| 132 | #define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) |
| 133 | |
| 134 | /******************************************************************************* |
| 135 | * GICv3 CPU interface registers & constants |
| 136 | ******************************************************************************/ |
| 137 | /* ICC_SRE bit definitions*/ |
| 138 | #define ICC_SRE_EN_BIT (1 << 3) |
| 139 | #define ICC_SRE_DIB_BIT (1 << 2) |
| 140 | #define ICC_SRE_DFB_BIT (1 << 1) |
| 141 | #define ICC_SRE_SRE_BIT (1 << 0) |
| 142 | |
| 143 | /* ICC_IGRPEN1_EL3 bit definitions */ |
| 144 | #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 |
| 145 | #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 |
| 146 | |
| 147 | #define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) |
| 148 | #define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) |
| 149 | |
| 150 | /* ICC_IGRPEN0_EL1 bit definitions */ |
| 151 | #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 |
| 152 | #define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) |
| 153 | |
| 154 | /* ICC_HPPIR0_EL1 bit definitions */ |
| 155 | #define HPPIR0_EL1_INTID_SHIFT 0 |
| 156 | #define HPPIR0_EL1_INTID_MASK 0xffffff |
| 157 | |
| 158 | /* ICC_HPPIR1_EL1 bit definitions */ |
| 159 | #define HPPIR1_EL1_INTID_SHIFT 0 |
| 160 | #define HPPIR1_EL1_INTID_MASK 0xffffff |
| 161 | |
| 162 | /* ICC_IAR0_EL1 bit definitions */ |
| 163 | #define IAR0_EL1_INTID_SHIFT 0 |
| 164 | #define IAR0_EL1_INTID_MASK 0xffffff |
| 165 | |
| 166 | /* ICC_IAR1_EL1 bit definitions */ |
| 167 | #define IAR1_EL1_INTID_SHIFT 0 |
| 168 | #define IAR1_EL1_INTID_MASK 0xffffff |
| 169 | |
| 170 | #ifndef __ASSEMBLY__ |
| 171 | |
| 172 | #include <stdint.h> |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 173 | #include <types.h> |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 174 | |
| 175 | #define gicv3_is_intr_id_special_identifier(id) \ |
| 176 | (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT)) |
| 177 | |
| 178 | /******************************************************************************* |
| 179 | * Helper GICv3 macros for SEL1 |
| 180 | ******************************************************************************/ |
| 181 | #define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\ |
| 182 | IAR1_EL1_INTID_MASK |
| 183 | #define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\ |
| 184 | HPPIR1_EL1_INTID_MASK |
| 185 | #define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id) |
| 186 | |
| 187 | |
| 188 | /******************************************************************************* |
| 189 | * Helper GICv3 macros for EL3 |
| 190 | ******************************************************************************/ |
| 191 | #define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\ |
| 192 | IAR0_EL1_INTID_MASK |
| 193 | #define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id) |
| 194 | |
| 195 | /******************************************************************************* |
| 196 | * This structure describes some of the implementation defined attributes of the |
| 197 | * GICv3 IP. It is used by the platform port to specify these attributes in order |
| 198 | * to initialise the GICV3 driver. The attributes are described below. |
| 199 | * |
| 200 | * 1. The 'gicd_base' field contains the base address of the Distributor |
| 201 | * interface programmer's view. |
| 202 | * |
| 203 | * 2. The 'gicr_base' field contains the base address of the Re-distributor |
| 204 | * interface programmer's view. |
| 205 | * |
| 206 | * 3. The 'g0_interrupt_array' field is a ponter to an array in which each |
| 207 | * entry corresponds to an ID of a Group 0 interrupt. |
| 208 | * |
| 209 | * 4. The 'g0_interrupt_num' field contains the number of entries in the |
| 210 | * 'g0_interrupt_array'. |
| 211 | * |
| 212 | * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each |
| 213 | * entry corresponds to an ID of a Group 1 interrupt. |
| 214 | * |
| 215 | * 6. The 'g1s_interrupt_num' field contains the number of entries in the |
| 216 | * 'g1s_interrupt_array'. |
| 217 | * |
| 218 | * 7. The 'rdistif_num' field contains the number of Redistributor interfaces |
| 219 | * the GIC implements. This is equal to the number of CPUs or CPU interfaces |
| 220 | * instantiated in the GIC. |
| 221 | * |
| 222 | * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry |
| 223 | * for storing the base address of the Redistributor interface frame of each |
| 224 | * CPU in the system. The size of the array = 'rdistif_num'. The base |
| 225 | * addresses are detected during driver initialisation. |
| 226 | * |
| 227 | * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the |
| 228 | * driver will use to convert an MPIDR value to a linear core index. This |
| 229 | * index will be used for accessing the 'rdistif_base_addrs' array. This is |
| 230 | * an optional field. A GICv3 implementation maps each MPIDR to a linear core |
| 231 | * index as well. This mapping can be found by reading the "Affinity Value" |
| 232 | * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the |
| 233 | * "Processor Numbers" are suitable to index into an array to access core |
| 234 | * specific information. If this not the case, the platform port must provide |
| 235 | * a hash function. Otherwise, the "Processor Number" field will be used to |
| 236 | * access the array elements. |
| 237 | ******************************************************************************/ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 238 | typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 239 | |
| 240 | typedef struct gicv3_driver_data { |
| 241 | uintptr_t gicd_base; |
| 242 | uintptr_t gicr_base; |
| 243 | unsigned int g0_interrupt_num; |
| 244 | unsigned int g1s_interrupt_num; |
| 245 | const unsigned int *g0_interrupt_array; |
| 246 | const unsigned int *g1s_interrupt_array; |
| 247 | unsigned int rdistif_num; |
| 248 | uintptr_t *rdistif_base_addrs; |
| 249 | mpidr_hash_fn mpidr_to_core_pos; |
| 250 | } gicv3_driver_data_t; |
| 251 | |
| 252 | /******************************************************************************* |
| 253 | * GICv3 EL3 driver API |
| 254 | ******************************************************************************/ |
| 255 | void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); |
| 256 | void gicv3_distif_init(void); |
| 257 | void gicv3_rdistif_init(unsigned int proc_num); |
| 258 | void gicv3_cpuif_enable(unsigned int proc_num); |
| 259 | void gicv3_cpuif_disable(unsigned int proc_num); |
| 260 | unsigned int gicv3_get_pending_interrupt_type(void); |
| 261 | unsigned int gicv3_get_pending_interrupt_id(void); |
| 262 | unsigned int gicv3_get_interrupt_type(unsigned int id, |
| 263 | unsigned int proc_num); |
| 264 | |
| 265 | |
| 266 | #endif /* __ASSEMBLY__ */ |
| 267 | #endif /* __GICV3_H__ */ |