Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <denver.h> |
| 35 | #include <mmio.h> |
| 36 | #include <platform.h> |
| 37 | #include <psci.h> |
| 38 | #include <pmc.h> |
| 39 | #include <tegra_def.h> |
| 40 | |
| 41 | #define SB_CSR 0x0 |
| 42 | #define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) |
| 43 | |
| 44 | /* AARCH64 CPU reset vector */ |
| 45 | #define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ |
| 46 | #define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ |
| 47 | |
| 48 | /* AARCH32 CPU reset vector */ |
| 49 | #define EVP_CPU_RESET_VECTOR 0x100 |
| 50 | |
| 51 | extern void tegra_secure_entrypoint(void); |
| 52 | |
| 53 | /* |
| 54 | * For T132, CPUs reset to AARCH32, so the reset vector is first |
| 55 | * armv8_trampoline which does a warm reset to AARCH64 and starts |
| 56 | * execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI. |
| 57 | */ |
| 58 | __aligned(8) const uint32_t armv8_trampoline[] = { |
| 59 | 0xE3A00003, /* mov r0, #3 */ |
| 60 | 0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */ |
| 61 | 0xEAFFFFFE, /* b . */ |
| 62 | }; |
| 63 | |
| 64 | /******************************************************************************* |
| 65 | * Setup secondary CPU vectors |
| 66 | ******************************************************************************/ |
| 67 | void plat_secondary_setup(void) |
| 68 | { |
| 69 | uint32_t val; |
| 70 | uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; |
| 71 | |
| 72 | /* |
| 73 | * For T132, CPUs reset to AARCH32, so the reset vector is first |
| 74 | * armv8_trampoline, which does a warm reset to AARCH64 and starts |
| 75 | * execution at the address in SCRATCH34/SCRATCH35. |
| 76 | */ |
| 77 | INFO("Setting up T132 CPU boot\n"); |
| 78 | |
| 79 | /* initial AARCH32 reset address */ |
| 80 | tegra_pmc_write_32(PMC_SECURE_SCRATCH22, |
| 81 | (unsigned long)&armv8_trampoline); |
| 82 | |
| 83 | /* set AARCH32 exception vector (read to flush) */ |
| 84 | mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR, |
| 85 | (unsigned long)&armv8_trampoline); |
| 86 | val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR); |
| 87 | |
| 88 | /* setup secondary CPU vector */ |
| 89 | mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, |
| 90 | (reset_addr & 0xFFFFFFFF) | 1); |
| 91 | val = reset_addr >> 32; |
| 92 | mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); |
| 93 | |
| 94 | /* configure PMC */ |
| 95 | tegra_pmc_cpu_setup(reset_addr); |
| 96 | tegra_pmc_lock_cpu_vectors(); |
| 97 | } |