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Soby Mathewe063d3c2015-10-07 09:45:27 +01001/*
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewe063d3c2015-10-07 09:45:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewe063d3c2015-10-07 09:45:27 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef GICV2_PRIVATE_H
8#define GICV2_PRIVATE_H
Soby Mathewe063d3c2015-10-07 09:45:27 +01009
10#include <gicv2.h>
11#include <mmio.h>
12#include <stdint.h>
13
14/*******************************************************************************
15 * Private function prototypes
16 ******************************************************************************/
17void gicv2_spis_configure_defaults(uintptr_t gicd_base);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010018void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
19 const interrupt_prop_t *interrupt_props,
20 unsigned int interrupt_props_num);
21void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
22 const interrupt_prop_t *interrupt_props,
23 unsigned int interrupt_props_num);
Soby Mathewe063d3c2015-10-07 09:45:27 +010024unsigned int gicv2_get_cpuif_id(uintptr_t base);
25
26/*******************************************************************************
27 * GIC Distributor interface accessors for reading entire registers
28 ******************************************************************************/
29static inline unsigned int gicd_read_pidr2(uintptr_t base)
30{
31 return mmio_read_32(base + GICD_PIDR2_GICV2);
32}
33
34/*******************************************************************************
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010035 * GIC Distributor interface accessors for writing entire registers
36 ******************************************************************************/
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010037static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id)
38{
39 return mmio_read_8(base + GICD_ITARGETSR + id);
40}
41
42static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id,
43 unsigned int target)
44{
Antonio Nino Diazca994e72018-08-21 10:02:33 +010045 uint8_t val = target & GIC_TARGET_CPU_MASK;
46
47 mmio_write_8(base + GICD_ITARGETSR + id, val);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010048}
49
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010050static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
51{
52 mmio_write_32(base + GICD_SGIR, val);
53}
54
55/*******************************************************************************
Soby Mathewe063d3c2015-10-07 09:45:27 +010056 * GIC CPU interface accessors for reading entire registers
57 ******************************************************************************/
58
59static inline unsigned int gicc_read_ctlr(uintptr_t base)
60{
61 return mmio_read_32(base + GICC_CTLR);
62}
63
64static inline unsigned int gicc_read_pmr(uintptr_t base)
65{
66 return mmio_read_32(base + GICC_PMR);
67}
68
69static inline unsigned int gicc_read_BPR(uintptr_t base)
70{
71 return mmio_read_32(base + GICC_BPR);
72}
73
74static inline unsigned int gicc_read_IAR(uintptr_t base)
75{
76 return mmio_read_32(base + GICC_IAR);
77}
78
79static inline unsigned int gicc_read_EOIR(uintptr_t base)
80{
81 return mmio_read_32(base + GICC_EOIR);
82}
83
84static inline unsigned int gicc_read_hppir(uintptr_t base)
85{
86 return mmio_read_32(base + GICC_HPPIR);
87}
88
89static inline unsigned int gicc_read_ahppir(uintptr_t base)
90{
91 return mmio_read_32(base + GICC_AHPPIR);
92}
93
94static inline unsigned int gicc_read_dir(uintptr_t base)
95{
96 return mmio_read_32(base + GICC_DIR);
97}
98
99static inline unsigned int gicc_read_iidr(uintptr_t base)
100{
101 return mmio_read_32(base + GICC_IIDR);
102}
103
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100104static inline unsigned int gicc_read_rpr(uintptr_t base)
105{
106 return mmio_read_32(base + GICC_RPR);
107}
108
Soby Mathewe063d3c2015-10-07 09:45:27 +0100109/*******************************************************************************
110 * GIC CPU interface accessors for writing entire registers
111 ******************************************************************************/
112
113static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
114{
115 mmio_write_32(base + GICC_CTLR, val);
116}
117
118static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
119{
120 mmio_write_32(base + GICC_PMR, val);
121}
122
123static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
124{
125 mmio_write_32(base + GICC_BPR, val);
126}
127
128
129static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
130{
131 mmio_write_32(base + GICC_IAR, val);
132}
133
134static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
135{
136 mmio_write_32(base + GICC_EOIR, val);
137}
138
139static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
140{
141 mmio_write_32(base + GICC_HPPIR, val);
142}
143
144static inline void gicc_write_dir(uintptr_t base, unsigned int val)
145{
146 mmio_write_32(base + GICC_DIR, val);
147}
148
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000149#endif /* GICV2_PRIVATE_H */