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Manoj Kumar9b4e3d72020-07-09 09:56:02 +01001/*
Manoj Kumarb7875952022-01-05 14:33:52 +00002 * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
Manoj Kumar9b4e3d72020-07-09 09:56:02 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <context.h>
10#include <cpu_macros.S>
11#include <cpuamu.h>
12#include <rainier.h>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
Manoj Kumar9b4e3d72020-07-09 09:56:02 +010024/* --------------------------------------------------
25 * Disable speculative loads if Rainier supports
26 * SSBS.
27 *
28 * Shall clobber: x0.
29 * --------------------------------------------------
30 */
31func rainier_disable_speculative_loads
32 /* Check if the PE implements SSBS */
33 mrs x0, id_aa64pfr1_el1
34 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
35 b.eq 1f
36
37 /* Disable speculative loads */
38 msr SSBS, xzr
39
401:
41 ret
42endfunc rainier_disable_speculative_loads
43
Manoj Kumarb7875952022-01-05 14:33:52 +000044 /* --------------------------------------------------
45 * Errata Workaround for Neoverse N1 Errata #1868343.
46 * This applies to revision <= r4p0 of Neoverse N1.
47 * This workaround is the same as the workaround for
48 * errata 1262606 and 1275112 but applies to a wider
49 * revision range.
50 * Rainier R0P0 is based on Neoverse N1 R4P0 so the
51 * workaround checks for r0p0 version of Rainier CPU.
52 * Inputs:
53 * x0: variant[4:7] and revision[0:3] of current cpu.
54 * Shall clobber: x0, x1 & x17
55 * --------------------------------------------------
56 */
57func errata_n1_1868343_wa
58 /*
59 * Compare x0 against revision r4p0
60 */
61 mov x17, x30
62 bl check_errata_1868343
63 cbz x0, 1f
64 mrs x1, RAINIER_CPUACTLR_EL1
65 orr x1, x1, RAINIER_CPUACTLR_EL1_BIT_13
66 msr RAINIER_CPUACTLR_EL1, x1
67 isb
681:
69 ret x17
70endfunc errata_n1_1868343_wa
71
72func check_errata_1868343
73 /* Applies to r0p0 of Rainier CPU */
74 mov x1, #0x00
75 b cpu_rev_var_ls
76endfunc check_errata_1868343
77
Manoj Kumar9b4e3d72020-07-09 09:56:02 +010078func rainier_reset_func
79 mov x19, x30
80
81 bl rainier_disable_speculative_loads
82
83 /* Forces all cacheable atomic instructions to be near */
84 mrs x0, RAINIER_CPUACTLR2_EL1
85 orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2
86 msr RAINIER_CPUACTLR2_EL1, x0
87 isb
88
89 bl cpu_get_rev_var
90 mov x18, x0
91
Manoj Kumarb7875952022-01-05 14:33:52 +000092#if ERRATA_N1_1868343
93 mov x0, x18
94 bl errata_n1_1868343_wa
95#endif
96
Manoj Kumar9b4e3d72020-07-09 09:56:02 +010097#if ENABLE_AMU
98 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
99 mrs x0, actlr_el3
100 orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
101 msr actlr_el3, x0
102
103 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
104 mrs x0, actlr_el2
105 orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
106 msr actlr_el2, x0
107
108 /* Enable group0 counters */
109 mov x0, #RAINIER_AMU_GROUP0_MASK
110 msr CPUAMCNTENSET_EL0, x0
111#endif
112
113 isb
114 ret x19
115endfunc rainier_reset_func
116
117 /* ---------------------------------------------
118 * HW will do the cache maintenance while powering down
119 * ---------------------------------------------
120 */
121func rainier_core_pwr_dwn
122 /* ---------------------------------------------
123 * Enable CPU power down bit in power control register
124 * ---------------------------------------------
125 */
126 mrs x0, RAINIER_CPUPWRCTLR_EL1
127 orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK
128 msr RAINIER_CPUPWRCTLR_EL1, x0
129 isb
130 ret
131endfunc rainier_core_pwr_dwn
132
133#if REPORT_ERRATA
134/*
135 * Errata printing function for Rainier. Must follow AAPCS.
136 */
137func rainier_errata_report
138 stp x8, x30, [sp, #-16]!
139
140 bl cpu_get_rev_var
141 mov x8, x0
142
Manoj Kumarb7875952022-01-05 14:33:52 +0000143 /*
144 * Report all errata. The revision-variant information is passed to
145 * checking functions of each errata.
146 */
147 report_errata ERRATA_N1_1868343, rainier, 1868343
148
Manoj Kumar9b4e3d72020-07-09 09:56:02 +0100149 ldp x8, x30, [sp], #16
150 ret
151endfunc rainier_errata_report
152#endif
Manoj Kumar9b4e3d72020-07-09 09:56:02 +0100153
154 /* ---------------------------------------------
155 * This function provides Rainier specific
156 * register information for crash reporting.
157 * It needs to return with x6 pointing to
158 * a list of register names in ascii and
159 * x8 - x15 having values of registers to be
160 * reported.
161 * ---------------------------------------------
162 */
163.section .rodata.rainier_regs, "aS"
164rainier_regs: /* The ascii list of register names to be reported */
165 .asciz "cpuectlr_el1", ""
166
167func rainier_cpu_reg_dump
168 adr x6, rainier_regs
169 mrs x8, RAINIER_CPUECTLR_EL1
170 ret
171endfunc rainier_cpu_reg_dump
172
Manoj Kumarfb4179c2021-01-27 16:29:03 +0000173declare_cpu_ops rainier, RAINIER_MIDR, \
Manoj Kumar9b4e3d72020-07-09 09:56:02 +0100174 rainier_reset_func, \
Manoj Kumar9b4e3d72020-07-09 09:56:02 +0100175 rainier_core_pwr_dwn