Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 1 | /* |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 6 | #ifndef NCORE_CCU_H |
| 7 | #define NCORE_CCU_H |
| 8 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 9 | #include <stdbool.h> |
| 10 | #include <stdint.h> |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 11 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 12 | #ifndef CCU_ACTIVATE_COH_FPGA |
| 13 | #define CCU_ACTIVATE_COH_FPGA 0 |
| 14 | #endif |
| 15 | // Address map for ccu init |
| 16 | #define addr_CAIUIDR1 (0x1C000000) |
| 17 | #define addr_GRBUNRRUCR (0x1c0ffff8) |
| 18 | #define base_addr_NRS_CAIU0 (0x1c000000) |
| 19 | #define base_addr_NRS_NCAIU0 (0x1c001000) |
| 20 | #define base_addr_NRS_NCAIU1 (0x1c002000) |
| 21 | #define base_addr_NRS_NCAIU2 (0x1c003000) |
| 22 | #define base_addr_NRS_NCAIU3 (0x1c004000) |
| 23 | #define base_addr_NRS_DCE0 (0x1c005000) |
| 24 | #define base_addr_NRS_DCE1 (0x1c006000) |
| 25 | //#define base_addr_NRS_DMI0 (0x1c007000) |
| 26 | //#define base_addr_NRS_DMI1 (0x1c008000) |
| 27 | //DMI |
| 28 | #define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR 0x1C007300 |
| 29 | #define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR 0x1C008300 |
| 30 | //DSU |
| 31 | #define ALT_CCU_DSU_CAIUAMIGR_ADDR 0x1C0003C0 |
| 32 | #define ALT_CCU_DSU_CAIUMIFSR_ADDR 0x1C0003C4 |
| 33 | #define ALT_CCU_DSU_CAIUGPRBLR1_ADDR 0x1C000414 |
| 34 | #define ALT_CCU_DSU_CAIUGPRBHR1_ADDR 0x1C000418 |
| 35 | #define ALT_CCU_DSU_CAIUGPRAR1_ADDR 0x1C000410 |
| 36 | #define ALT_CCU_DSU_CAIUGPRBLR2_ADDR 0x1C000424 |
| 37 | #define ALT_CCU_DSU_CAIUGPRBHR2_ADDR 0x1C000428 |
| 38 | #define ALT_CCU_DSU_CAIUGPRAR2_ADDR 0x1C000420 |
| 39 | #define ALT_CCU_DSU_CAIUGPRBLR4_ADDR 0x1C000444 |
| 40 | #define ALT_CCU_DSU_CAIUGPRBHR4_ADDR 0x1C000448 |
| 41 | #define ALT_CCU_DSU_CAIUGPRAR4_ADDR 0x1C000440 |
| 42 | #define ALT_CCU_DSU_CAIUGPRBLR5_ADDR 0x1C000454 |
| 43 | #define ALT_CCU_DSU_CAIUGPRBHR5_ADDR 0x1C000458 |
| 44 | #define ALT_CCU_DSU_CAIUGPRAR5_ADDR 0x1C000450 |
| 45 | #define ALT_CCU_DSU_CAIUGPRBLR6_ADDR 0x1C000464 |
| 46 | #define ALT_CCU_DSU_CAIUGPRBHR6_ADDR 0x1C000468 |
| 47 | #define ALT_CCU_DSU_CAIUGPRAR6_ADDR 0x1C000460 |
| 48 | #define ALT_CCU_DSU_CAIUGPRBLR7_ADDR 0x1C000474 |
| 49 | #define ALT_CCU_DSU_CAIUGPRBHR7_ADDR 0x1C000478 |
| 50 | #define ALT_CCU_DSU_CAIUGPRAR7_ADDR 0x1C000470 |
| 51 | #define ALT_CCU_DSU_CAIUGPRBLR8_ADDR 0x1C000484 |
| 52 | #define ALT_CCU_DSU_CAIUGPRBHR8_ADDR 0x1C000488 |
| 53 | #define ALT_CCU_DSU_CAIUGPRAR8_ADDR 0x1C000480 |
| 54 | #define ALT_CCU_DSU_CAIUGPRBLR9_ADDR 0x1C000494 |
| 55 | #define ALT_CCU_DSU_CAIUGPRBHR9_ADDR 0x1C000498 |
| 56 | #define ALT_CCU_DSU_CAIUGPRAR9_ADDR 0x1C000490 |
| 57 | #define ALT_CCU_DSU_CAIUGPRBLR10_ADDR 0x1C0004A4 |
| 58 | #define ALT_CCU_DSU_CAIUGPRBHR10_ADDR 0x1C0004A8 |
| 59 | #define ALT_CCU_DSU_CAIUGPRAR10_ADDR 0x1C0004A0 |
| 60 | //GIC |
| 61 | #define ALT_CCU_GIC_M_XAIUAMIGR_ADDR 0x1C0023C0 |
| 62 | #define ALT_CCU_GIC_M_XAIUMIFSR_ADDR 0x1C0023C4 |
| 63 | #define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR 0x1C002414 |
| 64 | #define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR 0x1C002418 |
| 65 | #define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR 0x1C002410 |
| 66 | #define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR 0x1C002464 |
| 67 | #define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR 0x1C002468 |
| 68 | #define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR 0x1C002460 |
| 69 | #define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR 0x1C002484 |
| 70 | #define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR 0x1C002488 |
| 71 | #define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR 0x1C002480 |
| 72 | #define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR 0x1C0024A4 |
| 73 | #define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR 0x1C0024A8 |
| 74 | #define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR 0x1C0024A0 |
| 75 | //FPGA2SOC |
| 76 | #define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR 0x1C0013C0 |
| 77 | #define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR 0x1C0013C4 |
| 78 | #define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR 0x1C001414 |
| 79 | #define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR 0x1C001418 |
| 80 | #define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR 0x1C001410 |
| 81 | #define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR 0x1C001464 |
| 82 | #define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR 0x1C001468 |
| 83 | #define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR 0x1C001460 |
| 84 | #define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR 0x1C001484 |
| 85 | #define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR 0x1C001488 |
| 86 | #define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR 0x1C001480 |
| 87 | #define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR 0x1C0014A4 |
| 88 | #define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR 0x1C0014A8 |
| 89 | #define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR 0x1C0014A0 |
| 90 | //TCU |
| 91 | #define ALT_CCU_TCU_BASE 0x1C003000 |
| 92 | #define ALT_CCU_TCU_XAIUAMIGR_ADDR ALT_CCU_TCU_BASE + 0x03C0 |
| 93 | #define ALT_CCU_TCU_XAIUMIFSR_ADDR ALT_CCU_TCU_BASE + 0x03C4 |
| 94 | #define ALT_CCU_TCU_XAIUGPRBLR0_ADDR ALT_CCU_TCU_BASE + 0x0404 |
| 95 | #define ALT_CCU_TCU_XAIUGPRBHR0_ADDR ALT_CCU_TCU_BASE + 0x0408 |
| 96 | #define ALT_CCU_TCU_XAIUGPRAR0_ADDR ALT_CCU_TCU_BASE + 0x0400 |
| 97 | #define ALT_CCU_TCU_XAIUGPRBLR1_ADDR ALT_CCU_TCU_BASE + 0x0414 |
| 98 | #define ALT_CCU_TCU_XAIUGPRBHR1_ADDR ALT_CCU_TCU_BASE + 0x0418 |
| 99 | #define ALT_CCU_TCU_XAIUGPRAR1_ADDR ALT_CCU_TCU_BASE + 0x0410 |
| 100 | #define ALT_CCU_TCU_XAIUGPRBLR2_ADDR ALT_CCU_TCU_BASE + 0x0424 |
| 101 | #define ALT_CCU_TCU_XAIUGPRBHR2_ADDR ALT_CCU_TCU_BASE + 0x0428 |
| 102 | #define ALT_CCU_TCU_XAIUGPRAR2_ADDR ALT_CCU_TCU_BASE + 0x0420 |
| 103 | #define ALT_CCU_TCU_XAIUGPRBLR6_ADDR 0x1C003464 |
| 104 | #define ALT_CCU_TCU_XAIUGPRBHR6_ADDR 0x1C003468 |
| 105 | #define ALT_CCU_TCU_XAIUGPRAR6_ADDR 0x1C003460 |
| 106 | #define ALT_CCU_TCU_XAIUGPRBLR8_ADDR 0x1C003484 |
| 107 | #define ALT_CCU_TCU_XAIUGPRBHR8_ADDR 0x1C003488 |
| 108 | #define ALT_CCU_TCU_XAIUGPRAR8_ADDR 0x1C003480 |
| 109 | #define ALT_CCU_TCU_XAIUGPRBLR10_ADDR 0x1C0034A4 |
| 110 | #define ALT_CCU_TCU_XAIUGPRBHR10_ADDR 0x1C0034A8 |
| 111 | #define ALT_CCU_TCU_XAIUGPRAR10_ADDR 0x1C0034A0 |
| 112 | //IOM |
| 113 | #define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR 0x1C0043C0 |
| 114 | #define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR 0x1C0013C4 |
| 115 | #define ALT_CCU_IOM_XAIUGPRBLR1_ADDR 0x1C001414 |
| 116 | #define ALT_CCU_IOM_XAIUGPRBHR1_ADDR 0x1C001418 |
| 117 | #define ALT_CCU_IOM_XAIUGPRAR1_ADDR 0x1C001410 |
| 118 | #define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR 0x1C001464 |
| 119 | #define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR 0x1C001468 |
| 120 | #define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR 0x1C001460 |
| 121 | #define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR 0x1C001484 |
| 122 | #define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR 0x1C001488 |
| 123 | #define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR 0x1C001480 |
| 124 | #define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR 0x1C0014A4 |
| 125 | #define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR 0x1C0014A8 |
| 126 | #define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR 0x1C0014A0 |
| 127 | //DCE |
| 128 | #define ALT_CCU_DCE0_DCEUAMIGR_ADDR 0x1C0053C0 |
| 129 | #define ALT_CCU_DCE0_DCEUMIFSR_ADDR 0x1C0053C4 |
| 130 | #define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR 0x1C005464 |
| 131 | #define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR 0x1C005468 |
| 132 | #define ALT_CCU_DCE0_DCEUGPRAR6_ADDR 0x1C005460 |
| 133 | #define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR 0x1C005484 |
| 134 | #define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR 0x1C005488 |
| 135 | #define ALT_CCU_DCE0_DCEUGPRAR8_ADDR 0x1C005480 |
| 136 | #define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR 0x1C0054A4 |
| 137 | #define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR 0x1C0054A8 |
| 138 | #define ALT_CCU_DCE0_DCEUGPRAR10_ADDR 0x1C0054A0 |
| 139 | #define ALT_CCU_DCE1_DCEUAMIGR_ADDR 0x1C0063C0 |
| 140 | #define ALT_CCU_DCE1_DCEUMIFSR_ADDR 0x1C0063C4 |
| 141 | #define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR 0x1C006464 |
| 142 | #define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR 0x1C006468 |
| 143 | #define ALT_CCU_DCE1_DCEUGPRAR6_ADDR 0x1C006460 |
| 144 | #define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR 0x1C006484 |
| 145 | #define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR 0x1C006488 |
| 146 | #define ALT_CCU_DCE1_DCEUGPRAR8_ADDR 0x1C006480 |
| 147 | #define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR 0x1C0064A4 |
| 148 | #define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR 0x1C0064A8 |
| 149 | #define ALT_CCU_DCE1_DCEUGPRAR10_ADDR 0x1C0064A0 |
| 150 | #define offset_NRS_GPRAR0 (0x400) |
| 151 | #define offset_NRS_GPRBLR0 (0x404) |
| 152 | #define offset_NRS_GPRBHR0 (0x408) |
| 153 | #define offset_NRS_GPRAR1 (0x410) |
| 154 | #define offset_NRS_GPRBLR1 (0x414) |
| 155 | #define offset_NRS_GPRBHR1 (0x418) |
| 156 | #define offset_NRS_GPRAR2 (0x420) |
| 157 | #define offset_NRS_GPRBLR2 (0x424) |
| 158 | #define offset_NRS_GPRBHR2 (0x428) |
| 159 | #define offset_NRS_GPRAR3 (0x430) |
| 160 | #define offset_NRS_GPRBLR3 (0x434) |
| 161 | #define offset_NRS_GPRBHR3 (0x438) |
| 162 | #define offset_NRS_GPRAR4 (0x440) |
| 163 | #define offset_NRS_GPRBLR4 (0x444) |
| 164 | #define offset_NRS_GPRBHR4 (0x448) |
| 165 | #define offset_NRS_GPRAR5 (0x450) |
| 166 | #define offset_NRS_GPRBLR5 (0x454) |
| 167 | #define offset_NRS_GPRBHR5 (0x458) |
| 168 | #define offset_NRS_GPRAR6 (0x460) |
| 169 | #define offset_NRS_GPRBLR6 (0x464) |
| 170 | #define offset_NRS_GPRBHR6 (0x468) |
| 171 | #define offset_NRS_GPRAR7 (0x470) |
| 172 | #define offset_NRS_GPRBLR7 (0x474) |
| 173 | #define offset_NRS_GPRBHR7 (0x478) |
| 174 | #define offset_NRS_GPRAR8 (0x480) |
| 175 | #define offset_NRS_GPRBLR8 (0x484) |
| 176 | #define offset_NRS_GPRBHR8 (0x488) |
| 177 | #define offset_NRS_GPRAR9 (0x490) |
| 178 | #define offset_NRS_GPRBLR9 (0x494) |
| 179 | #define offset_NRS_GPRBHR9 (0x498) |
| 180 | #define offset_NRS_GPRAR10 (0x4a0) |
| 181 | #define offset_NRS_GPRBLR10 (0x4a4) |
| 182 | #define offset_NRS_GPRBHR10 (0x4a8) |
| 183 | #define offset_NRS_AMIGR (0x3c0) |
| 184 | #define offset_NRS_MIFSR (0x3c4) |
| 185 | #define offset_NRS_DMIUSMCTCR (0x300) |
| 186 | #define base_addr_DII0_PSSPERIPHS (0x10000) |
| 187 | #define base_addr_DII0_LWHPS2FPGA (0x20000) |
| 188 | #define base_addr_DII0_HPS2FPGA_1G (0x40000) |
| 189 | #define base_addr_DII0_HPS2FPGA_15G (0x400000) |
| 190 | #define base_addr_DII0_HPS2FPGA_240G (0x4000000) |
| 191 | #define base_addr_DII1_MPFEREGS (0x18000) |
| 192 | #define base_addr_DII2_GICREGS (0x1D000) |
| 193 | #define base_addr_DII3_OCRAM (0x0) |
| 194 | #define base_addr_BHR (0x0) |
| 195 | #define base_addr_DMI_SDRAM_2G (0x80000) |
| 196 | #define base_addr_DMI_SDRAM_30G (0x800000) |
| 197 | #define base_addr_DMI_SDRAM_480G (0x8000000) |
| 198 | // ((0x0<<9) | (0xf<<20) | (0x1<<30) | (0x1<<31)) |
| 199 | #define wr_DII0_PSSPERIPHS 0xC0F00000 |
| 200 | // ((0x0<<9) | (0x11<<20) | (0x1<<30) | (0x1<<31)) |
| 201 | #define wr_DII0_LWHPS2FPGA 0xC1100000 |
| 202 | // ((0x0<<9) | (0x12<<20) | (0x1<<30) | (0x1<<31)) |
| 203 | #define wr_DII0_HPS2FPGA_1G 0xC1200000 |
| 204 | // ((0x0<<9) | (0x16<<20) | (0x1<<30) | (0x1<<31)) |
| 205 | #define wr_DII0_HPS2FPGA_15G 0xC1600000 |
| 206 | // ((0x0<<9) | (0x1a<<20) | (0x1<<30) | (0x1<<31)) |
| 207 | #define wr_DII0_HPS2FPGA_240G 0xC1A00000 |
| 208 | // ((0x1<<9) | (0xe<<20) | (0x1<<30) | (0x1<<31)) |
| 209 | #define wr_DII1_MPFEREGS 0xC0E00200 |
| 210 | // ((0x2<<9) | (0x8<<20) | (0x1<<30) | (0x1<<31)) |
| 211 | #define wr_DII2_GICREGS 0xC0800400 |
| 212 | // ((0x3<<9) | (0x9<<20) | (0x1<<30) | (0x1<<31)) |
| 213 | #define wr_DII3_OCRAM 0xC0900600 |
| 214 | // ((0x0<<9) | (0x12<<20) | (0x0<<30) | (0x1<<31)) |
| 215 | #define wr_DMI_SDRAM_1G_ORDERED 0x81200000 |
| 216 | // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x12<<20) | (0x0<<30) | (0x1<<31)) |
| 217 | #define wr_DMI_SDRAM_1G 0x81200006 |
| 218 | // ((0x0<<9) | (0x13<<20) | (0x0<<30) | (0x1<<31)) |
| 219 | #define wr_DMI_SDRAM_2G_ORDERED 0x81300000 |
| 220 | // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x13<<20) | (0x0<<30) | (0x1<<31)) |
| 221 | #define wr_DMI_SDRAM_2G 0x81300006 |
| 222 | // ((0x0<<9) | (0x16<<20) | (0x0<<30) | (0x1<<31)) |
| 223 | #define wr_DMI_SDRAM_15G_ORDERED 0x81600000 |
| 224 | // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x16<<20) | (0x0<<30) | (0x1<<31)) |
| 225 | #define wr_DMI_SDRAM_15G 0x81600006 |
| 226 | // ((0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31)) |
| 227 | #define wr_DMI_SDRAM_30G_ORDERED 0x81700000 |
| 228 | // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31)) |
| 229 | #define wr_DMI_SDRAM_30G 0x81700006 |
| 230 | // ((0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31)) |
| 231 | #define wr_DMI_SDRAM_240G_ORDERED 0x81a00000 |
| 232 | // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31)) |
| 233 | #define wr_DMI_SDRAM_240G 0x81a00006 |
| 234 | // ((0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31)) |
| 235 | #define wr_DMI_SDRAM_480G_ORDERED 0x81b00000 |
| 236 | // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31)) |
| 237 | #define wr_DMI_SDRAM_480G 0x81b00006 |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 238 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 239 | typedef enum CCU_REGION_SECURITY_e { |
| 240 | // |
| 241 | // Allow secure accesses only. |
| 242 | // |
| 243 | CCU_REGION_SECURITY_SECURE_ONLY, |
| 244 | // |
| 245 | // Allow non-secure accesses only. |
| 246 | // |
| 247 | CCU_REGION_SECURITY_NON_SECURE_ONLY, |
| 248 | // |
| 249 | // Allow accesses of any security state. |
| 250 | // |
| 251 | CCU_REGION_SECURITY_DONT_CARE |
| 252 | } CCU_REGION_SECURITY_t; |
| 253 | typedef enum CCU_REGION_PRIVILEGE_e { |
| 254 | // |
| 255 | // Allow privileged accesses only. |
| 256 | // |
| 257 | CCU_REGION_PRIVILEGE_PRIVILEGED_ONLY, |
| 258 | // |
| 259 | // Allow unprivileged accesses only. |
| 260 | // |
| 261 | CCU_REGION_PRIVILEGE_NON_PRIVILEGED_ONLY, |
| 262 | // |
| 263 | // Allow accesses of any privilege. |
| 264 | // |
| 265 | CCU_REGION_PRIVILEGE_DONT_CARE |
| 266 | } CCU_REGION_PRIVILEGE_t; |
| 267 | // |
| 268 | // Initializes the CCU by enabling all regions except RAM 1 - 5. |
| 269 | // This is needed because of an RTL change around 2016.02.24. |
| 270 | // |
| 271 | // Runtime measurement: |
| 272 | // - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32) |
| 273 | // - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf) |
| 274 | // |
| 275 | // Runtime history: |
| 276 | // - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32) |
| 277 | // - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf) |
| 278 | // |
| 279 | int ccu_hps_init(void); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 280 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 281 | typedef enum ccu_hps_ram_region_e { |
| 282 | ccu_hps_ram_region_ramspace0 = 0, |
| 283 | ccu_hps_ram_region_ramspace1 = 1, |
| 284 | ccu_hps_ram_region_ramspace2 = 2, |
| 285 | ccu_hps_ram_region_ramspace3 = 3, |
| 286 | ccu_hps_ram_region_ramspace4 = 4, |
| 287 | ccu_hps_ram_region_ramspace5 = 5, |
| 288 | } ccu_hps_ram_region_t; |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 289 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 290 | // Disables a RAM (OCRAM) region with the given ID. |
| 291 | int ccu_hps_ram_region_disable(int id); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 292 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 293 | // Enables a RAM (OCRAM) region with the given ID. |
| 294 | int ccu_hps_ram_region_enable(int id); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 295 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 296 | // Attempts to remap a RAM (OCRAM) region with the given ID to span the given |
| 297 | // start and end address. It also assigns the security and privilege policy. |
| 298 | // Regions must be a power-of-two size with a minimum size of 64B. |
| 299 | int ccu_hps_ram_region_remap(int id, uintptr_t start, uintptr_t end, |
| 300 | CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 301 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 302 | // Verifies that all enabled RAM (OCRAM) regions does not overlap. |
| 303 | int ccu_hps_ram_validate(void); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 304 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 305 | typedef enum ccu_hps_mem_region_e { |
| 306 | ccu_hps_mem_region_ddrspace0 = 0, |
| 307 | ccu_hps_mem_region_memspace0 = 1, |
| 308 | ccu_hps_mem_region_memspace1a = 2, |
| 309 | ccu_hps_mem_region_memspace1b = 3, |
| 310 | ccu_hps_mem_region_memspace1c = 4, |
| 311 | ccu_hps_mem_region_memspace1d = 5, |
| 312 | ccu_hps_mem_region_memspace1e = 6, |
| 313 | } ccu_hps_mem_region_t; |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 314 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 315 | // Disables mem0 (DDR) region with the given ID. |
| 316 | int ccu_hps_mem0_region_disable(int id); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 317 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 318 | // Enables mem0 (DDR) region with the given ID. |
| 319 | int ccu_hps_mem0_region_enable(int id); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 320 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 321 | // Attempts to remap mem0 (DDR) region with the given ID to span the given |
| 322 | // start and end address. It also assigns the security nad privlege policy. |
| 323 | // Regions must be a power-of-two in size with a minimum size of 64B. |
| 324 | int ccu_hps_mem0_region_remap(int id, uintptr_t start, uintptr_t end, |
| 325 | CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 326 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 327 | // Verifies that all enabled mem0 (DDR) regions does not overlap. |
| 328 | int ccu_hps_mem0_validate(void); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 329 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 330 | typedef enum ccu_hps_ios_region_e { |
| 331 | ccu_hps_ios_region_iospace0a = 0, |
| 332 | ccu_hps_ios_region_iospace0b = 1, |
| 333 | ccu_hps_ios_region_iospace1a = 2, |
| 334 | ccu_hps_ios_region_iospace1b = 3, |
| 335 | ccu_hps_ios_region_iospace1c = 4, |
| 336 | ccu_hps_ios_region_iospace1d = 5, |
| 337 | ccu_hps_ios_region_iospace1e = 6, |
| 338 | ccu_hps_ios_region_iospace1f = 7, |
| 339 | ccu_hps_ios_region_iospace1g = 8, |
| 340 | ccu_hps_ios_region_iospace2a = 9, |
| 341 | ccu_hps_ios_region_iospace2b = 10, |
| 342 | ccu_hps_ios_region_iospace2c = 11, |
| 343 | } ccu_hps_ios_region_t; |
| 344 | |
| 345 | // Disables the IOS (IO Slave) region with the given ID. |
| 346 | int ccu_hps_ios_region_disable(int id); |
| 347 | |
| 348 | // Enables the IOS (IO Slave) region with the given ID. |
| 349 | int ccu_hps_ios_region_enable(int id); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 350 | |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 351 | |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 352 | #define NCORE_CCU_OFFSET 0xf7000000 |
| 353 | |
| 354 | /* Coherent Sub-System Address Map */ |
| 355 | #define NCORE_CAIU_OFFSET 0x00000 |
| 356 | #define NCORE_CAIU_SIZE 0x01000 |
| 357 | #define NCORE_NCBU_OFFSET 0x60000 |
| 358 | #define NCORE_NCBU_SIZE 0x01000 |
| 359 | #define NCORE_DIRU_OFFSET 0x80000 |
| 360 | #define NCORE_DIRU_SIZE 0x01000 |
| 361 | #define NCORE_CMIU_OFFSET 0xc0000 |
| 362 | #define NCORE_CMIU_SIZE 0x01000 |
| 363 | #define NCORE_CSR_OFFSET 0xff000 |
| 364 | #define NCORE_CSADSERO 0x00040 |
| 365 | #define NCORE_CSUIDR 0x00ff8 |
| 366 | #define NCORE_CSIDR 0x00ffc |
| 367 | /* Directory Unit Register Map */ |
| 368 | #define NCORE_DIRUSFER 0x00010 |
| 369 | #define NCORE_DIRUMRHER 0x00070 |
| 370 | #define NCORE_DIRUSFMCR 0x00080 |
| 371 | #define NCORE_DIRUSFMAR 0x00084 |
| 372 | /* Coherent Agent Interface Unit Register Map */ |
| 373 | #define NCORE_CAIUIDR 0x00ffc |
| 374 | /* Snoop Enable Register */ |
| 375 | #define NCORE_DIRUCASER0 0x00040 |
| 376 | #define NCORE_DIRUCASER1 0x00044 |
| 377 | #define NCORE_DIRUCASER2 0x00048 |
| 378 | #define NCORE_DIRUCASER3 0x0004c |
| 379 | #define NCORE_CSADSER0 0x00040 |
| 380 | #define NCORE_CSADSER1 0x00044 |
| 381 | #define NCORE_CSADSER2 0x00048 |
| 382 | #define NCORE_CSADSER3 0x0004c |
| 383 | /* Protocols Definition */ |
| 384 | #define ACE_W_DVM 0 |
| 385 | #define ACE_L_W_DVM 1 |
| 386 | #define ACE_WO_DVM 2 |
| 387 | #define ACE_L_WO_DVM 3 |
| 388 | /* Bypass OC Ram Firewall */ |
| 389 | #define NCORE_FW_OCRAM_BLK_BASE 0x100200 |
| 390 | #define NCORE_FW_OCRAM_BLK_CGF1 0x04 |
| 391 | #define NCORE_FW_OCRAM_BLK_CGF2 0x08 |
| 392 | #define NCORE_FW_OCRAM_BLK_CGF3 0x0c |
| 393 | #define NCORE_FW_OCRAM_BLK_CGF4 0x10 |
| 394 | #define OCRAM_PRIVILEGED_MASK BIT(29) |
| 395 | #define OCRAM_SECURE_MASK BIT(30) |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 396 | /* Macros */ |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 397 | #define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base)) |
| 398 | #define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 399 | + (reg)) |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 400 | #define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 401 | + (reg)) |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 402 | #define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 403 | + (reg)) |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 404 | #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 405 | + NCORE_DIRU_SIZE * (x)) |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 406 | #define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 407 | + NCORE_CAIU_SIZE * (x)) |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 408 | #define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\ |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 409 | + (reg)) |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 410 | #define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24) |
| 411 | #define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16) |
| 412 | #define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8) |
| 413 | #define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0) |
| 414 | #define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18) |
| 415 | #define SNOOP_FILTER_ID(x) (((x) << 16)) |
| 416 | #define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) |
| 417 | #define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16) |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 418 | |
| 419 | typedef struct coh_ss_id { |
| 420 | uint8_t num_coh_mem; |
| 421 | uint8_t num_directory; |
| 422 | uint8_t num_non_coh_bridge; |
| 423 | uint8_t num_coh_agent; |
| 424 | uint8_t num_snoop_filter; |
| 425 | } coh_ss_id_t; |
| 426 | |
| 427 | uint32_t init_ncore_ccu(void); |
Boon Khai Ng | 1e5550b | 2021-05-21 22:56:37 +0800 | [diff] [blame] | 428 | void ncore_enable_ocram_firewall(void); |
Jit Loon Lim | 17d0762 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 429 | void setup_smmu_stream_id(void); |
Hadi Asyrafi | 073e70d | 2019-06-17 12:30:22 +0800 | [diff] [blame] | 430 | |
| 431 | #endif |