Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 1 | /* |
Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <platform_def.h> |
Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 8 | |
| 9 | #include <nrd_ras.h> |
| 10 | #include <nrd_sdei.h> |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 11 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame^] | 12 | struct nrd_ras_ev_map plat_ras_map[] = { |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 13 | /* Non Secure base RAM ECC CE interrupt */ |
| 14 | {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI}, |
| 15 | |
| 16 | /* Non Secure base RAM ECC UE interrupt */ |
| 17 | {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI}, |
Omkar Anand Kulkarni | 67f5ccb | 2023-06-21 13:11:04 +0530 | [diff] [blame] | 18 | |
| 19 | /* CPU 1-bit ECC CE error interrupt */ |
| 20 | {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI} |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 21 | }; |
| 22 | |
| 23 | /* RAS error record list definition, used by the common RAS framework. */ |
| 24 | struct err_record_info plat_err_records[] = { |
| 25 | /* Base element RAM Non-secure error record. */ |
| 26 | ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL, |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame^] | 27 | &nrd_ras_sram_intr_handler, 0), |
| 28 | ERR_RECORD_SYSREG_V1(0, 1, NULL, &nrd_ras_cpu_intr_handler, 0), |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | /* RAS error interrupt list definition, used by the common RAS framework. */ |
| 32 | struct ras_interrupt plat_ras_interrupts[] = { |
| 33 | { |
Omkar Anand Kulkarni | 67f5ccb | 2023-06-21 13:11:04 +0530 | [diff] [blame] | 34 | .intr_number = PLAT_CORE_FAULT_IRQ, |
| 35 | .err_record = &plat_err_records[1], |
| 36 | }, { |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 37 | .intr_number = NS_RAM_ECC_CE_INT, |
| 38 | .err_record = &plat_err_records[0], |
| 39 | }, { |
| 40 | .intr_number = NS_RAM_ECC_UE_INT, |
| 41 | .err_record = &plat_err_records[0], |
| 42 | }, |
| 43 | }; |
| 44 | |
| 45 | /* Registers the RAS error record list with common RAS framework. */ |
| 46 | REGISTER_ERR_RECORD_INFO(plat_err_records); |
| 47 | /* Registers the RAS error interrupt info list with common RAS framework. */ |
| 48 | REGISTER_RAS_INTERRUPTS(plat_ras_interrupts); |
| 49 | |
| 50 | /* Platform RAS handling config data definition */ |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame^] | 51 | struct plat_nrd_ras_config ras_config = { |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 52 | plat_ras_map, |
| 53 | ARRAY_SIZE(plat_ras_map) |
| 54 | }; |