Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <context.h> |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 36 | #include <context_mgmt.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 37 | #include <debug.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 38 | #include <platform.h> |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 39 | #include <string.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 40 | #include "psci_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 42 | /* |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 43 | * SPD power management operations, expected to be supplied by the registered |
| 44 | * SPD on successful SP initialization |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 45 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 46 | const spd_pm_ops_t *psci_spd_pm; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 47 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 48 | /* |
| 49 | * PSCI requested local power state map. This array is used to store the local |
| 50 | * power states requested by a CPU for power levels from level 1 to |
| 51 | * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power |
| 52 | * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a |
| 53 | * CPU are the same. |
| 54 | * |
| 55 | * During state coordination, the platform is passed an array containing the |
| 56 | * local states requested for a particular non cpu power domain by each cpu |
| 57 | * within the domain. |
| 58 | * |
| 59 | * TODO: Dense packing of the requested states will cause cache thrashing |
| 60 | * when multiple power domains write to it. If we allocate the requested |
| 61 | * states at each power level in a cache-line aligned per-domain memory, |
| 62 | * the cache thrashing can be avoided. |
| 63 | */ |
| 64 | static plat_local_state_t |
| 65 | psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; |
| 66 | |
| 67 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 68 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 69 | * Arrays that hold the platform's power domain tree information for state |
| 70 | * management of power domains. |
| 71 | * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain |
| 72 | * which is an ancestor of a CPU power domain. |
| 73 | * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 74 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 75 | non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 76 | #if USE_COHERENT_MEM |
| 77 | __attribute__ ((section("tzfw_coherent_mem"))) |
| 78 | #endif |
| 79 | ; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 80 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 81 | cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; |
| 82 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 84 | * Pointer to functions exported by the platform to complete power mgmt. ops |
| 85 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 86 | const plat_psci_ops_t *psci_plat_pm_ops; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 87 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 88 | /****************************************************************************** |
| 89 | * Check that the maximum power level supported by the platform makes sense |
| 90 | *****************************************************************************/ |
| 91 | CASSERT(PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL && \ |
| 92 | PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \ |
| 93 | assert_platform_max_pwrlvl_check); |
Soby Mathew | 2b7de2b | 2015-02-12 14:45:02 +0000 | [diff] [blame] | 94 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 95 | /* |
| 96 | * The plat_local_state used by the platform is one of these types: RUN, |
| 97 | * RETENTION and OFF. The platform can define further sub-states for each type |
| 98 | * apart from RUN. This categorization is done to verify the sanity of the |
| 99 | * psci_power_state passed by the platform and to print debug information. The |
| 100 | * categorization is done on the basis of the following conditions: |
| 101 | * |
| 102 | * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN. |
| 103 | * |
| 104 | * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is |
| 105 | * STATE_TYPE_RETN. |
| 106 | * |
| 107 | * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is |
| 108 | * STATE_TYPE_OFF. |
| 109 | */ |
| 110 | typedef enum plat_local_state_type { |
| 111 | STATE_TYPE_RUN = 0, |
| 112 | STATE_TYPE_RETN, |
| 113 | STATE_TYPE_OFF |
| 114 | } plat_local_state_type_t; |
| 115 | |
| 116 | /* The macro used to categorize plat_local_state. */ |
| 117 | #define find_local_state_type(plat_local_state) \ |
| 118 | ((plat_local_state) ? ((plat_local_state > PLAT_MAX_RET_STATE) \ |
| 119 | ? STATE_TYPE_OFF : STATE_TYPE_RETN) \ |
| 120 | : STATE_TYPE_RUN) |
| 121 | |
| 122 | /****************************************************************************** |
| 123 | * Check that the maximum retention level supported by the platform is less |
| 124 | * than the maximum off level. |
| 125 | *****************************************************************************/ |
| 126 | CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, \ |
| 127 | assert_platform_max_off_and_retn_state_check); |
| 128 | |
| 129 | /****************************************************************************** |
| 130 | * This function ensures that the power state parameter in a CPU_SUSPEND request |
| 131 | * is valid. If so, it returns the requested states for each power level. |
| 132 | *****************************************************************************/ |
| 133 | int psci_validate_power_state(unsigned int power_state, |
| 134 | psci_power_state_t *state_info) |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 135 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 136 | /* Check SBZ bits in power state are zero */ |
| 137 | if (psci_check_power_state(power_state)) |
| 138 | return PSCI_E_INVALID_PARAMS; |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 139 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 140 | assert(psci_plat_pm_ops->validate_power_state); |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 141 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 142 | /* Validate the power_state using platform pm_ops */ |
| 143 | return psci_plat_pm_ops->validate_power_state(power_state, state_info); |
| 144 | } |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 145 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 146 | /****************************************************************************** |
| 147 | * This function retrieves the `psci_power_state_t` for system suspend from |
| 148 | * the platform. |
| 149 | *****************************************************************************/ |
| 150 | void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) |
| 151 | { |
| 152 | /* |
| 153 | * Assert that the required pm_ops hook is implemented to ensure that |
| 154 | * the capability detected during psci_setup() is valid. |
| 155 | */ |
| 156 | assert(psci_plat_pm_ops->get_sys_suspend_power_state); |
| 157 | |
| 158 | /* |
| 159 | * Query the platform for the power_state required for system suspend |
| 160 | */ |
| 161 | psci_plat_pm_ops->get_sys_suspend_power_state(state_info); |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | /******************************************************************************* |
Soby Mathew | 9616838 | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 165 | * This function verifies that the all the other cores in the system have been |
| 166 | * turned OFF and the current CPU is the last running CPU in the system. |
| 167 | * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) |
| 168 | * otherwise. |
| 169 | ******************************************************************************/ |
| 170 | unsigned int psci_is_last_on_cpu(void) |
| 171 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 172 | unsigned int cpu_idx, my_idx = plat_my_core_pos(); |
Soby Mathew | 9616838 | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 173 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 174 | for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { |
| 175 | if (cpu_idx == my_idx) { |
| 176 | assert(psci_get_aff_info_state() == AFF_STATE_ON); |
Soby Mathew | 9616838 | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 177 | continue; |
| 178 | } |
| 179 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 180 | if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) |
Soby Mathew | 9616838 | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | return 1; |
| 185 | } |
| 186 | |
| 187 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 188 | * Routine to return the maximum power level to traverse to after a cpu has |
| 189 | * been physically powered up. It is expected to be called immediately after |
| 190 | * reset from assembler code. |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 191 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 192 | static unsigned int get_power_on_target_pwrlvl(void) |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 193 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 194 | unsigned int pwrlvl; |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 195 | |
| 196 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 197 | * Assume that this cpu was suspended and retrieve its target power |
| 198 | * level. If it is invalid then it could only have been turned off |
| 199 | * earlier. PLAT_MAX_PWR_LVL will be the highest power level a |
| 200 | * cpu can be turned off to. |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 201 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 202 | pwrlvl = psci_get_suspend_pwrlvl(); |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 203 | if (pwrlvl == PSCI_INVALID_PWR_LVL) |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 204 | pwrlvl = PLAT_MAX_PWR_LVL; |
| 205 | return pwrlvl; |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 206 | } |
| 207 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 208 | /****************************************************************************** |
| 209 | * Helper function to update the requested local power state array. This array |
| 210 | * does not store the requested state for the CPU power level. Hence an |
| 211 | * assertion is added to prevent us from accessing the wrong index. |
| 212 | *****************************************************************************/ |
| 213 | static void psci_set_req_local_pwr_state(unsigned int pwrlvl, |
| 214 | unsigned int cpu_idx, |
| 215 | plat_local_state_t req_pwr_state) |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 216 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 217 | assert(pwrlvl > PSCI_CPU_PWR_LVL); |
| 218 | psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state; |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 219 | } |
| 220 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 221 | /****************************************************************************** |
| 222 | * This function initializes the psci_req_local_pwr_states. |
| 223 | *****************************************************************************/ |
| 224 | void psci_init_req_local_pwr_states(void) |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 225 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 226 | /* Initialize the requested state of all non CPU power domains as OFF */ |
| 227 | memset(&psci_req_local_pwr_states, PLAT_MAX_OFF_STATE, |
| 228 | sizeof(psci_req_local_pwr_states)); |
| 229 | } |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 230 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 231 | /****************************************************************************** |
| 232 | * Helper function to return a reference to an array containing the local power |
| 233 | * states requested by each cpu for a power domain at 'pwrlvl'. The size of the |
| 234 | * array will be the number of cpu power domains of which this power domain is |
| 235 | * an ancestor. These requested states will be used to determine a suitable |
| 236 | * target state for this power domain during psci state coordination. An |
| 237 | * assertion is added to prevent us from accessing the CPU power level. |
| 238 | *****************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 239 | static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, |
| 240 | unsigned int cpu_idx) |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 241 | { |
| 242 | assert(pwrlvl > PSCI_CPU_PWR_LVL); |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 243 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 244 | return &psci_req_local_pwr_states[pwrlvl - 1][cpu_idx]; |
| 245 | } |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 246 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 247 | /****************************************************************************** |
| 248 | * Helper function to return the current local power state of each power domain |
| 249 | * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This |
| 250 | * function will be called after a cpu is powered on to find the local state |
| 251 | * each power domain has emerged from. |
| 252 | *****************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 253 | static void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 254 | psci_power_state_t *target_state) |
| 255 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 256 | unsigned int parent_idx, lvl; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 257 | plat_local_state_t *pd_state = target_state->pwr_domain_state; |
| 258 | |
| 259 | pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); |
| 260 | parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; |
| 261 | |
| 262 | /* Copy the local power state from node to state_info */ |
| 263 | for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { |
| 264 | #if !USE_COHERENT_MEM |
| 265 | /* |
| 266 | * If using normal memory for psci_non_cpu_pd_nodes, we need |
| 267 | * to flush before reading the local power state as another |
| 268 | * cpu in the same power domain could have updated it and this |
| 269 | * code runs before caches are enabled. |
| 270 | */ |
| 271 | flush_dcache_range( |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 272 | (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 273 | sizeof(psci_non_cpu_pd_nodes[parent_idx])); |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 274 | #endif |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 275 | pd_state[lvl] = psci_non_cpu_pd_nodes[parent_idx].local_state; |
| 276 | parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; |
| 277 | } |
| 278 | |
| 279 | /* Set the the higher levels to RUN */ |
| 280 | for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) |
| 281 | target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; |
| 282 | } |
| 283 | |
| 284 | /****************************************************************************** |
| 285 | * Helper function to set the target local power state that each power domain |
| 286 | * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will |
| 287 | * enter. This function will be called after coordination of requested power |
| 288 | * states has been done for each power level. |
| 289 | *****************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 290 | static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 291 | const psci_power_state_t *target_state) |
| 292 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 293 | unsigned int parent_idx, lvl; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 294 | const plat_local_state_t *pd_state = target_state->pwr_domain_state; |
| 295 | |
| 296 | psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 297 | |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 298 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 299 | * Need to flush as local_state will be accessed with Data Cache |
| 300 | * disabled during power on |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 301 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 302 | flush_cpu_data(psci_svc_cpu_data.local_state); |
| 303 | |
| 304 | parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; |
| 305 | |
| 306 | /* Copy the local_state from state_info */ |
| 307 | for (lvl = 1; lvl <= end_pwrlvl; lvl++) { |
| 308 | psci_non_cpu_pd_nodes[parent_idx].local_state = pd_state[lvl]; |
| 309 | #if !USE_COHERENT_MEM |
| 310 | flush_dcache_range( |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 311 | (uintptr_t)&psci_non_cpu_pd_nodes[parent_idx], |
| 312 | sizeof(psci_non_cpu_pd_nodes[parent_idx])); |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 313 | #endif |
| 314 | parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; |
| 315 | } |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 316 | } |
| 317 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 318 | |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 319 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 320 | * PSCI helper function to get the parent nodes corresponding to a cpu_index. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 321 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 322 | void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 323 | unsigned int end_lvl, |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 324 | unsigned int node_index[]) |
| 325 | { |
| 326 | unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; |
| 327 | int i; |
| 328 | |
| 329 | for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { |
| 330 | *node_index++ = parent_node; |
| 331 | parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node; |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | /****************************************************************************** |
| 336 | * This function is invoked post CPU power up and initialization. It sets the |
| 337 | * affinity info state, target power state and requested power state for the |
| 338 | * current CPU and all its ancestor power domains to RUN. |
| 339 | *****************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 340 | void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl) |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 341 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 342 | unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 343 | parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; |
| 344 | |
| 345 | /* Reset the local_state to RUN for the non cpu power domains. */ |
| 346 | for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { |
| 347 | psci_non_cpu_pd_nodes[parent_idx].local_state = |
| 348 | PSCI_LOCAL_STATE_RUN; |
| 349 | #if !USE_COHERENT_MEM |
| 350 | flush_dcache_range( |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 351 | (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 352 | sizeof(psci_non_cpu_pd_nodes[parent_idx])); |
| 353 | #endif |
| 354 | psci_set_req_local_pwr_state(lvl, |
| 355 | cpu_idx, |
| 356 | PSCI_LOCAL_STATE_RUN); |
| 357 | parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; |
| 358 | } |
| 359 | |
| 360 | /* Set the affinity info state to ON */ |
| 361 | psci_set_aff_info_state(AFF_STATE_ON); |
| 362 | |
| 363 | psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); |
| 364 | flush_cpu_data(psci_svc_cpu_data); |
| 365 | } |
| 366 | |
| 367 | /****************************************************************************** |
| 368 | * This function is passed the local power states requested for each power |
| 369 | * domain (state_info) between the current CPU domain and its ancestors until |
| 370 | * the target power level (end_pwrlvl). It updates the array of requested power |
| 371 | * states with this information. |
| 372 | * |
| 373 | * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it |
| 374 | * retrieves the states requested by all the cpus of which the power domain at |
| 375 | * that level is an ancestor. It passes this information to the platform to |
| 376 | * coordinate and return the target power state. If the target state for a level |
| 377 | * is RUN then subsequent levels are not considered. At the CPU level, state |
| 378 | * coordination is not required. Hence, the requested and the target states are |
| 379 | * the same. |
| 380 | * |
| 381 | * The 'state_info' is updated with the target state for each level between the |
| 382 | * CPU and the 'end_pwrlvl' and returned to the caller. |
| 383 | * |
| 384 | * This function will only be invoked with data cache enabled and while |
| 385 | * powering down a core. |
| 386 | *****************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 387 | void psci_do_state_coordination(unsigned int end_pwrlvl, |
| 388 | psci_power_state_t *state_info) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 389 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 390 | unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); |
| 391 | unsigned int start_idx, ncpus; |
| 392 | plat_local_state_t target_state, *req_states; |
| 393 | |
| 394 | parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; |
| 395 | |
| 396 | /* For level 0, the requested state will be equivalent |
| 397 | to target state */ |
| 398 | for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { |
| 399 | |
| 400 | /* First update the requested power state */ |
| 401 | psci_set_req_local_pwr_state(lvl, cpu_idx, |
| 402 | state_info->pwr_domain_state[lvl]); |
| 403 | |
| 404 | /* Get the requested power states for this power level */ |
| 405 | start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; |
| 406 | req_states = psci_get_req_local_pwr_states(lvl, start_idx); |
| 407 | |
| 408 | /* |
| 409 | * Let the platform coordinate amongst the requested states at |
| 410 | * this power level and return the target local power state. |
| 411 | */ |
| 412 | ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; |
| 413 | target_state = plat_get_target_pwr_state(lvl, |
| 414 | req_states, |
| 415 | ncpus); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 416 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 417 | state_info->pwr_domain_state[lvl] = target_state; |
| 418 | |
| 419 | /* Break early if the negotiated target power state is RUN */ |
| 420 | if (is_local_state_run(state_info->pwr_domain_state[lvl])) |
| 421 | break; |
| 422 | |
| 423 | parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; |
| 424 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 425 | |
| 426 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 427 | * This is for cases when we break out of the above loop early because |
| 428 | * the target power state is RUN at a power level < end_pwlvl. |
| 429 | * We update the requested power state from state_info and then |
| 430 | * set the target state as RUN. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 431 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 432 | for (lvl = lvl + 1; lvl <= end_pwrlvl; lvl++) { |
| 433 | psci_set_req_local_pwr_state(lvl, cpu_idx, |
| 434 | state_info->pwr_domain_state[lvl]); |
| 435 | state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 436 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 437 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 438 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 439 | /* Update the target state in the power domain nodes */ |
| 440 | psci_set_target_local_pwr_states(end_pwrlvl, state_info); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 441 | } |
| 442 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 443 | /****************************************************************************** |
| 444 | * This function validates a suspend request by making sure that if a standby |
| 445 | * state is requested then no power level is turned off and the highest power |
| 446 | * level is placed in a standby/retention state. |
| 447 | * |
| 448 | * It also ensures that the state level X will enter is not shallower than the |
| 449 | * state level X + 1 will enter. |
| 450 | * |
| 451 | * This validation will be enabled only for DEBUG builds as the platform is |
| 452 | * expected to perform these validations as well. |
| 453 | *****************************************************************************/ |
| 454 | int psci_validate_suspend_req(const psci_power_state_t *state_info, |
| 455 | unsigned int is_power_down_state) |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 456 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 457 | unsigned int max_off_lvl, target_lvl, max_retn_lvl; |
| 458 | plat_local_state_t state; |
| 459 | plat_local_state_type_t req_state_type, deepest_state_type; |
| 460 | int i; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 461 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 462 | /* Find the target suspend power level */ |
| 463 | target_lvl = psci_find_target_suspend_lvl(state_info); |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 464 | if (target_lvl == PSCI_INVALID_PWR_LVL) |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 465 | return PSCI_E_INVALID_PARAMS; |
| 466 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 467 | /* All power domain levels are in a RUN state to begin with */ |
| 468 | deepest_state_type = STATE_TYPE_RUN; |
| 469 | |
| 470 | for (i = target_lvl; i >= PSCI_CPU_PWR_LVL; i--) { |
| 471 | state = state_info->pwr_domain_state[i]; |
| 472 | req_state_type = find_local_state_type(state); |
| 473 | |
| 474 | /* |
| 475 | * While traversing from the highest power level to the lowest, |
| 476 | * the state requested for lower levels has to be the same or |
| 477 | * deeper i.e. equal to or greater than the state at the higher |
| 478 | * levels. If this condition is true, then the requested state |
| 479 | * becomes the deepest state encountered so far. |
| 480 | */ |
| 481 | if (req_state_type < deepest_state_type) |
| 482 | return PSCI_E_INVALID_PARAMS; |
| 483 | deepest_state_type = req_state_type; |
| 484 | } |
| 485 | |
| 486 | /* Find the highest off power level */ |
| 487 | max_off_lvl = psci_find_max_off_lvl(state_info); |
| 488 | |
| 489 | /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 490 | max_retn_lvl = PSCI_INVALID_PWR_LVL; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 491 | if (target_lvl != max_off_lvl) |
| 492 | max_retn_lvl = target_lvl; |
| 493 | |
| 494 | /* |
| 495 | * If this is not a request for a power down state then max off level |
| 496 | * has to be invalid and max retention level has to be a valid power |
| 497 | * level. |
| 498 | */ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 499 | if (!is_power_down_state && (max_off_lvl != PSCI_INVALID_PWR_LVL || |
| 500 | max_retn_lvl == PSCI_INVALID_PWR_LVL)) |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 501 | return PSCI_E_INVALID_PARAMS; |
| 502 | |
| 503 | return PSCI_E_SUCCESS; |
| 504 | } |
| 505 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 506 | /****************************************************************************** |
| 507 | * This function finds the highest power level which will be powered down |
| 508 | * amongst all the power levels specified in the 'state_info' structure |
| 509 | *****************************************************************************/ |
| 510 | unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) |
Achin Gupta | cab78e4 | 2014-07-28 00:09:01 +0100 | [diff] [blame] | 511 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 512 | int i; |
Achin Gupta | cab78e4 | 2014-07-28 00:09:01 +0100 | [diff] [blame] | 513 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 514 | for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { |
| 515 | if (is_local_state_off(state_info->pwr_domain_state[i])) |
| 516 | return i; |
| 517 | } |
| 518 | |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 519 | return PSCI_INVALID_PWR_LVL; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 520 | } |
| 521 | |
| 522 | /****************************************************************************** |
| 523 | * This functions finds the level of the highest power domain which will be |
| 524 | * placed in a low power state during a suspend operation. |
| 525 | *****************************************************************************/ |
| 526 | unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) |
| 527 | { |
| 528 | int i; |
| 529 | |
| 530 | for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { |
| 531 | if (!is_local_state_run(state_info->pwr_domain_state[i])) |
| 532 | return i; |
Achin Gupta | cab78e4 | 2014-07-28 00:09:01 +0100 | [diff] [blame] | 533 | } |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 534 | |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 535 | return PSCI_INVALID_PWR_LVL; |
Achin Gupta | cab78e4 | 2014-07-28 00:09:01 +0100 | [diff] [blame] | 536 | } |
| 537 | |
| 538 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 539 | * This function is passed a cpu_index and the highest level in the topology |
| 540 | * tree that the operation should be applied to. It picks up locks in order of |
| 541 | * increasing power domain level in the range specified. |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 542 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 543 | void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, |
| 544 | unsigned int cpu_idx) |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 545 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 546 | unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 547 | unsigned int level; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 548 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 549 | /* No locking required for level 0. Hence start locking from level 1 */ |
| 550 | for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) { |
| 551 | psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); |
| 552 | parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 553 | } |
| 554 | } |
| 555 | |
| 556 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 557 | * This function is passed a cpu_index and the highest level in the topology |
| 558 | * tree that the operation should be applied to. It releases the locks in order |
| 559 | * of decreasing power domain level in the range specified. |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 560 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 561 | void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, |
| 562 | unsigned int cpu_idx) |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 563 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 564 | unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0}; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 565 | int level; |
| 566 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 567 | /* Get the parent nodes */ |
| 568 | psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 569 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 570 | /* Unlock top down. No unlocking required for level 0. */ |
| 571 | for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1; level--) { |
| 572 | parent_idx = parent_nodes[level - 1]; |
| 573 | psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 574 | } |
| 575 | } |
| 576 | |
| 577 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 578 | * Simple routine to determine whether a mpidr is valid or not. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 579 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 580 | int psci_validate_mpidr(u_register_t mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 581 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 582 | if (plat_core_pos_by_mpidr(mpidr) < 0) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 583 | return PSCI_E_INVALID_PARAMS; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 584 | |
| 585 | return PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 586 | } |
| 587 | |
| 588 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 589 | * This function determines the full entrypoint information for the requested |
Soby Mathew | 8595b87 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 590 | * PSCI entrypoint on power on/resume and returns it. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 591 | ******************************************************************************/ |
Soby Mathew | f1f97a1 | 2015-07-15 12:13:26 +0100 | [diff] [blame] | 592 | static int psci_get_ns_ep_info(entry_point_info_t *ep, |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 593 | uintptr_t entrypoint, |
| 594 | u_register_t context_id) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 595 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 596 | unsigned long ep_attr, sctlr; |
| 597 | unsigned int daif, ee, mode; |
| 598 | unsigned long ns_scr_el3 = read_scr_el3(); |
| 599 | unsigned long ns_sctlr_el1 = read_sctlr_el1(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 600 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 601 | sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; |
| 602 | ee = 0; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 603 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 604 | ep_attr = NON_SECURE | EP_ST_DISABLE; |
| 605 | if (sctlr & SCTLR_EE_BIT) { |
| 606 | ep_attr |= EP_EE_BIG; |
| 607 | ee = 1; |
| 608 | } |
Soby Mathew | 8595b87 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 609 | SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 610 | |
Soby Mathew | 8595b87 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 611 | ep->pc = entrypoint; |
| 612 | memset(&ep->args, 0, sizeof(ep->args)); |
| 613 | ep->args.arg0 = context_id; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 614 | |
| 615 | /* |
| 616 | * Figure out whether the cpu enters the non-secure address space |
| 617 | * in aarch32 or aarch64 |
| 618 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 619 | if (ns_scr_el3 & SCR_RW_BIT) { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 620 | |
| 621 | /* |
| 622 | * Check whether a Thumb entry point has been provided for an |
| 623 | * aarch64 EL |
| 624 | */ |
| 625 | if (entrypoint & 0x1) |
Soby Mathew | f1f97a1 | 2015-07-15 12:13:26 +0100 | [diff] [blame] | 626 | return PSCI_E_INVALID_ADDRESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 627 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 628 | mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 629 | |
Soby Mathew | 8595b87 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 630 | ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 631 | } else { |
| 632 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 633 | mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 634 | |
| 635 | /* |
| 636 | * TODO: Choose async. exception bits if HYP mode is not |
| 637 | * implemented according to the values of SCR.{AW, FW} bits |
| 638 | */ |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 639 | daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; |
| 640 | |
Soby Mathew | 8595b87 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 641 | ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 642 | } |
| 643 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 644 | return PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | /******************************************************************************* |
Soby Mathew | f1f97a1 | 2015-07-15 12:13:26 +0100 | [diff] [blame] | 648 | * This function validates the entrypoint with the platform layer if the |
| 649 | * appropriate pm_ops hook is exported by the platform and returns the |
| 650 | * 'entry_point_info'. |
| 651 | ******************************************************************************/ |
| 652 | int psci_validate_entry_point(entry_point_info_t *ep, |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 653 | uintptr_t entrypoint, |
| 654 | u_register_t context_id) |
Soby Mathew | f1f97a1 | 2015-07-15 12:13:26 +0100 | [diff] [blame] | 655 | { |
| 656 | int rc; |
| 657 | |
| 658 | /* Validate the entrypoint using platform psci_ops */ |
| 659 | if (psci_plat_pm_ops->validate_ns_entrypoint) { |
| 660 | rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); |
| 661 | if (rc != PSCI_E_SUCCESS) |
| 662 | return PSCI_E_INVALID_ADDRESS; |
| 663 | } |
| 664 | |
| 665 | /* |
| 666 | * Verify and derive the re-entry information for |
| 667 | * the non-secure world from the non-secure state from |
| 668 | * where this call originated. |
| 669 | */ |
| 670 | rc = psci_get_ns_ep_info(ep, entrypoint, context_id); |
| 671 | return rc; |
| 672 | } |
| 673 | |
| 674 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 675 | * Generic handler which is called when a cpu is physically powered on. It |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 676 | * traverses the node information and finds the highest power level powered |
| 677 | * off and performs generic, architectural, platform setup and state management |
| 678 | * to power on that power level and power levels below it. |
| 679 | * e.g. For a cpu that's been powered on, it will call the platform specific |
| 680 | * code to enable the gic cpu interface and for a cluster it will enable |
| 681 | * coherency at the interconnect level in addition to gic cpu interface. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 682 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 683 | void psci_power_up_finish(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 684 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 685 | unsigned int end_pwrlvl, cpu_idx = plat_my_core_pos(); |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 686 | psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 687 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 688 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 689 | * Verify that we have been explicitly turned ON or resumed from |
| 690 | * suspend. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 691 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 692 | if (psci_get_aff_info_state() == AFF_STATE_OFF) { |
| 693 | ERROR("Unexpected affinity info state"); |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 694 | panic(); |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 695 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 696 | |
| 697 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 698 | * Get the maximum power domain level to traverse to after this cpu |
| 699 | * has been physically powered up. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 700 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 701 | end_pwrlvl = get_power_on_target_pwrlvl(); |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 702 | |
| 703 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 704 | * This function acquires the lock corresponding to each power level so |
| 705 | * that by the time all locks are taken, the system topology is snapshot |
| 706 | * and state management can be done safely. |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 707 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 708 | psci_acquire_pwr_domain_locks(end_pwrlvl, |
| 709 | cpu_idx); |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 710 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 711 | psci_get_target_local_pwr_states(end_pwrlvl, &state_info); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 712 | |
| 713 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 714 | * This CPU could be resuming from suspend or it could have just been |
| 715 | * turned on. To distinguish between these 2 cases, we examine the |
| 716 | * affinity state of the CPU: |
| 717 | * - If the affinity state is ON_PENDING then it has just been |
| 718 | * turned on. |
| 719 | * - Else it is resuming from suspend. |
| 720 | * |
| 721 | * Depending on the type of warm reset identified, choose the right set |
| 722 | * of power management handler and perform the generic, architecture |
| 723 | * and platform specific handling. |
Achin Gupta | cab78e4 | 2014-07-28 00:09:01 +0100 | [diff] [blame] | 724 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 725 | if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) |
| 726 | psci_cpu_on_finish(cpu_idx, &state_info); |
| 727 | else |
| 728 | psci_cpu_suspend_finish(cpu_idx, &state_info); |
Achin Gupta | cab78e4 | 2014-07-28 00:09:01 +0100 | [diff] [blame] | 729 | |
| 730 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 731 | * Set the requested and target state of this CPU and all the higher |
| 732 | * power domains which are ancestors of this CPU to run. |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 733 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 734 | psci_set_pwr_domains_to_run(end_pwrlvl); |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 735 | |
| 736 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 737 | * This loop releases the lock corresponding to each power level |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 738 | * in the reverse order to which they were acquired. |
| 739 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 740 | psci_release_pwr_domain_locks(end_pwrlvl, |
| 741 | cpu_idx); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 742 | } |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 743 | |
| 744 | /******************************************************************************* |
| 745 | * This function initializes the set of hooks that PSCI invokes as part of power |
| 746 | * management operation. The power management hooks are expected to be provided |
| 747 | * by the SPD, after it finishes all its initialization |
| 748 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 749 | void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 750 | { |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 751 | assert(pm); |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 752 | psci_spd_pm = pm; |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 753 | |
| 754 | if (pm->svc_migrate) |
| 755 | psci_caps |= define_psci_cap(PSCI_MIG_AARCH64); |
| 756 | |
| 757 | if (pm->svc_migrate_info) |
| 758 | psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) |
| 759 | | define_psci_cap(PSCI_MIG_INFO_TYPE); |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 760 | } |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 761 | |
| 762 | /******************************************************************************* |
Soby Mathew | 110fe36 | 2014-10-23 10:35:34 +0100 | [diff] [blame] | 763 | * This function invokes the migrate info hook in the spd_pm_ops. It performs |
| 764 | * the necessary return value validation. If the Secure Payload is UP and |
| 765 | * migrate capable, it returns the mpidr of the CPU on which the Secure payload |
| 766 | * is resident through the mpidr parameter. Else the value of the parameter on |
| 767 | * return is undefined. |
| 768 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 769 | int psci_spd_migrate_info(u_register_t *mpidr) |
Soby Mathew | 110fe36 | 2014-10-23 10:35:34 +0100 | [diff] [blame] | 770 | { |
| 771 | int rc; |
| 772 | |
| 773 | if (!psci_spd_pm || !psci_spd_pm->svc_migrate_info) |
| 774 | return PSCI_E_NOT_SUPPORTED; |
| 775 | |
| 776 | rc = psci_spd_pm->svc_migrate_info(mpidr); |
| 777 | |
| 778 | assert(rc == PSCI_TOS_UP_MIG_CAP || rc == PSCI_TOS_NOT_UP_MIG_CAP \ |
| 779 | || rc == PSCI_TOS_NOT_PRESENT_MP || rc == PSCI_E_NOT_SUPPORTED); |
| 780 | |
| 781 | return rc; |
| 782 | } |
| 783 | |
| 784 | |
| 785 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 786 | * This function prints the state of all power domains present in the |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 787 | * system |
| 788 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 789 | void psci_print_power_domain_map(void) |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 790 | { |
| 791 | #if LOG_LEVEL >= LOG_LEVEL_INFO |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 792 | unsigned int idx; |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 793 | plat_local_state_t state; |
| 794 | plat_local_state_type_t state_type; |
| 795 | |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 796 | /* This array maps to the PSCI_STATE_X definitions in psci.h */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 797 | static const char *psci_state_type_str[] = { |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 798 | "ON", |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 799 | "RETENTION", |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 800 | "OFF", |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 801 | }; |
| 802 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 803 | INFO("PSCI Power Domain Map:\n"); |
| 804 | for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); |
| 805 | idx++) { |
| 806 | state_type = find_local_state_type( |
| 807 | psci_non_cpu_pd_nodes[idx].local_state); |
| 808 | INFO(" Domain Node : Level %u, parent_node %d," |
| 809 | " State %s (0x%x)\n", |
| 810 | psci_non_cpu_pd_nodes[idx].level, |
| 811 | psci_non_cpu_pd_nodes[idx].parent_node, |
| 812 | psci_state_type_str[state_type], |
| 813 | psci_non_cpu_pd_nodes[idx].local_state); |
| 814 | } |
| 815 | |
| 816 | for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { |
| 817 | state = psci_get_cpu_local_state_by_idx(idx); |
| 818 | state_type = find_local_state_type(state); |
| 819 | INFO(" CPU Node : MPID 0x%lx, parent_node %d," |
| 820 | " State %s (0x%x)\n", |
| 821 | psci_cpu_pd_nodes[idx].mpidr, |
| 822 | psci_cpu_pd_nodes[idx].parent_node, |
| 823 | psci_state_type_str[state_type], |
| 824 | psci_get_cpu_local_state_by_idx(idx)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 825 | } |
| 826 | #endif |
| 827 | } |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 828 | |
| 829 | #if ENABLE_PLAT_COMPAT |
| 830 | /******************************************************************************* |
| 831 | * PSCI Compatibility helper function to return the 'power_state' parameter of |
| 832 | * the PSCI CPU SUSPEND request for the current CPU. Returns PSCI_INVALID_DATA |
| 833 | * if not invoked within CPU_SUSPEND for the current CPU. |
| 834 | ******************************************************************************/ |
| 835 | int psci_get_suspend_powerstate(void) |
| 836 | { |
| 837 | /* Sanity check to verify that CPU is within CPU_SUSPEND */ |
| 838 | if (psci_get_aff_info_state() == AFF_STATE_ON && |
| 839 | !is_local_state_run(psci_get_cpu_local_state())) |
| 840 | return psci_power_state_compat[plat_my_core_pos()]; |
| 841 | |
| 842 | return PSCI_INVALID_DATA; |
| 843 | } |
| 844 | |
| 845 | /******************************************************************************* |
| 846 | * PSCI Compatibility helper function to return the state id of the current |
| 847 | * cpu encoded in the 'power_state' parameter. Returns PSCI_INVALID_DATA |
| 848 | * if not invoked within CPU_SUSPEND for the current CPU. |
| 849 | ******************************************************************************/ |
| 850 | int psci_get_suspend_stateid(void) |
| 851 | { |
| 852 | unsigned int power_state; |
| 853 | power_state = psci_get_suspend_powerstate(); |
| 854 | if (power_state != PSCI_INVALID_DATA) |
| 855 | return psci_get_pstate_id(power_state); |
| 856 | |
| 857 | return PSCI_INVALID_DATA; |
| 858 | } |
| 859 | |
| 860 | /******************************************************************************* |
| 861 | * PSCI Compatibility helper function to return the state id encoded in the |
| 862 | * 'power_state' parameter of the CPU specified by 'mpidr'. Returns |
| 863 | * PSCI_INVALID_DATA if the CPU is not in CPU_SUSPEND. |
| 864 | ******************************************************************************/ |
| 865 | int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr) |
| 866 | { |
| 867 | int cpu_idx = plat_core_pos_by_mpidr(mpidr); |
| 868 | |
| 869 | if (cpu_idx == -1) |
| 870 | return PSCI_INVALID_DATA; |
| 871 | |
| 872 | /* Sanity check to verify that the CPU is in CPU_SUSPEND */ |
| 873 | if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_ON && |
| 874 | !is_local_state_run(psci_get_cpu_local_state_by_idx(cpu_idx))) |
| 875 | return psci_get_pstate_id(psci_power_state_compat[cpu_idx]); |
| 876 | |
| 877 | return PSCI_INVALID_DATA; |
| 878 | } |
| 879 | |
| 880 | /******************************************************************************* |
| 881 | * This function returns highest affinity level which is in OFF |
| 882 | * state. The affinity instance with which the level is associated is |
| 883 | * determined by the caller. |
| 884 | ******************************************************************************/ |
| 885 | unsigned int psci_get_max_phys_off_afflvl(void) |
| 886 | { |
| 887 | psci_power_state_t state_info; |
| 888 | |
| 889 | memset(&state_info, 0, sizeof(state_info)); |
| 890 | psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info); |
| 891 | |
| 892 | return psci_find_target_suspend_lvl(&state_info); |
| 893 | } |
| 894 | |
| 895 | /******************************************************************************* |
| 896 | * PSCI Compatibility helper function to return target affinity level requested |
| 897 | * for the CPU_SUSPEND. This function assumes affinity levels correspond to |
| 898 | * power domain levels on the platform. |
| 899 | ******************************************************************************/ |
| 900 | int psci_get_suspend_afflvl(void) |
| 901 | { |
| 902 | return psci_get_suspend_pwrlvl(); |
| 903 | } |
| 904 | |
| 905 | #endif |