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Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
Soby Mathewda43b662015-07-08 21:45:46 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta7c88f3f2014-02-18 18:09:12 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta7c88f3f2014-02-18 18:09:12 +000031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <bl_common.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000033#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010034#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010035#include <platform_def.h>
Dan Handley4fd2f5c2014-08-04 11:41:20 +010036#include <platform_tsp.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000037#include <spinlock.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <tsp.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010039#include "tsp_private.h"
Achin Gupta7c88f3f2014-02-18 18:09:12 +000040
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010041
42/*******************************************************************************
Achin Gupta7c88f3f2014-02-18 18:09:12 +000043 * Lock to control access to the console
44 ******************************************************************************/
45spinlock_t console_lock;
46
47/*******************************************************************************
48 * Per cpu data structure to populate parameters for an SMC in C code and use
49 * a pointer to this structure in assembler code to populate x0-x7
50 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010051static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT];
Achin Gupta7c88f3f2014-02-18 18:09:12 +000052
53/*******************************************************************************
54 * Per cpu data structure to keep track of TSP activity
55 ******************************************************************************/
Achin Gupta76717892014-05-09 11:42:56 +010056work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
Achin Gupta7c88f3f2014-02-18 18:09:12 +000057
58/*******************************************************************************
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010059 * The BL32 memory footprint starts with an RO sections and ends
Soby Mathew2ae20432015-01-08 18:02:44 +000060 * with the linker symbol __BL32_END__. Use it to find the memory size
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010061 ******************************************************************************/
62#define BL32_TOTAL_BASE (unsigned long)(&__RO_START__)
63
Soby Mathew2ae20432015-01-08 18:02:44 +000064#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__)
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010065
Dan Handleye2712bc2014-04-10 15:37:22 +010066static tsp_args_t *set_smc_args(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +000067 uint64_t arg1,
68 uint64_t arg2,
69 uint64_t arg3,
70 uint64_t arg4,
71 uint64_t arg5,
72 uint64_t arg6,
73 uint64_t arg7)
74{
Achin Gupta7c88f3f2014-02-18 18:09:12 +000075 uint32_t linear_id;
Dan Handleye2712bc2014-04-10 15:37:22 +010076 tsp_args_t *pcpu_smc_args;
Achin Gupta7c88f3f2014-02-18 18:09:12 +000077
78 /*
79 * Return to Secure Monitor by raising an SMC. The results of the
80 * service are passed as an arguments to the SMC
81 */
Soby Mathewda43b662015-07-08 21:45:46 +010082 linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +000083 pcpu_smc_args = &tsp_smc_args[linear_id];
84 write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0);
85 write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1);
86 write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2);
87 write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3);
88 write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4);
89 write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5);
90 write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6);
91 write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7);
92
93 return pcpu_smc_args;
94}
95
96/*******************************************************************************
97 * TSP main entry point where it gets the opportunity to initialize its secure
98 * state/applications. Once the state is initialized, it must return to the
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010099 * SPD with a pointer to the 'tsp_vector_table' jump table.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000100 ******************************************************************************/
101uint64_t tsp_main(void)
102{
Dan Handley91b624e2014-07-29 17:14:00 +0100103 NOTICE("TSP: %s\n", version_string);
104 NOTICE("TSP: %s\n", build_message);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000105 INFO("TSP: Total memory base : 0x%lx\n", BL32_TOTAL_BASE);
106 INFO("TSP: Total memory size : 0x%lx bytes\n",
107 BL32_TOTAL_LIMIT - BL32_TOTAL_BASE);
Dan Handley91b624e2014-07-29 17:14:00 +0100108
Soby Mathewda43b662015-07-08 21:45:46 +0100109 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000110
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000111 /* Initialize the platform */
Dan Handley4fd2f5c2014-08-04 11:41:20 +0100112 tsp_platform_setup();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000113
114 /* Initialize secure/applications state here */
Achin Guptabbc33f22014-05-09 13:33:42 +0100115 tsp_generic_timer_start();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000116
117 /* Update this cpu's statistics */
118 tsp_stats[linear_id].smc_count++;
119 tsp_stats[linear_id].eret_count++;
120 tsp_stats[linear_id].cpu_on_count++;
121
Dan Handley91b624e2014-07-29 17:14:00 +0100122#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000123 spin_lock(&console_lock);
Soby Mathewda43b662015-07-08 21:45:46 +0100124 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
125 read_mpidr(),
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000126 tsp_stats[linear_id].smc_count,
127 tsp_stats[linear_id].eret_count,
128 tsp_stats[linear_id].cpu_on_count);
129 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100130#endif
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100131 return (uint64_t) &tsp_vector_table;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000132}
133
134/*******************************************************************************
135 * This function performs any remaining book keeping in the test secure payload
136 * after this cpu's architectural state has been setup in response to an earlier
137 * psci cpu_on request.
138 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100139tsp_args_t *tsp_cpu_on_main(void)
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000140{
Soby Mathewda43b662015-07-08 21:45:46 +0100141 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000142
Achin Guptabbc33f22014-05-09 13:33:42 +0100143 /* Initialize secure/applications state here */
144 tsp_generic_timer_start();
145
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000146 /* Update this cpu's statistics */
147 tsp_stats[linear_id].smc_count++;
148 tsp_stats[linear_id].eret_count++;
149 tsp_stats[linear_id].cpu_on_count++;
150
Dan Handley91b624e2014-07-29 17:14:00 +0100151#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000152 spin_lock(&console_lock);
Soby Mathewda43b662015-07-08 21:45:46 +0100153 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
154 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
155 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100156 tsp_stats[linear_id].smc_count,
157 tsp_stats[linear_id].eret_count,
158 tsp_stats[linear_id].cpu_on_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000159 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100160#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000161 /* Indicate to the SPD that we have completed turned ourselves on */
162 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
163}
164
165/*******************************************************************************
166 * This function performs any remaining book keeping in the test secure payload
167 * before this cpu is turned off in response to a psci cpu_off request.
168 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100169tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000170 uint64_t arg1,
171 uint64_t arg2,
172 uint64_t arg3,
173 uint64_t arg4,
174 uint64_t arg5,
175 uint64_t arg6,
176 uint64_t arg7)
177{
Soby Mathewda43b662015-07-08 21:45:46 +0100178 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000179
Achin Guptabbc33f22014-05-09 13:33:42 +0100180 /*
181 * This cpu is being turned off, so disable the timer to prevent the
182 * secure timer interrupt from interfering with power down. A pending
183 * interrupt will be lost but we do not care as we are turning off.
184 */
185 tsp_generic_timer_stop();
186
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000187 /* Update this cpu's statistics */
188 tsp_stats[linear_id].smc_count++;
189 tsp_stats[linear_id].eret_count++;
190 tsp_stats[linear_id].cpu_off_count++;
191
Dan Handley91b624e2014-07-29 17:14:00 +0100192#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000193 spin_lock(&console_lock);
Soby Mathewda43b662015-07-08 21:45:46 +0100194 INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
195 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
196 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100197 tsp_stats[linear_id].smc_count,
198 tsp_stats[linear_id].eret_count,
199 tsp_stats[linear_id].cpu_off_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000200 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100201#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000202
Achin Gupta607084e2014-02-09 18:24:19 +0000203 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000204 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
205}
206
207/*******************************************************************************
208 * This function performs any book keeping in the test secure payload before
209 * this cpu's architectural state is saved in response to an earlier psci
210 * cpu_suspend request.
211 ******************************************************************************/
Soby Mathewf5121572014-09-30 11:19:51 +0100212tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000213 uint64_t arg1,
214 uint64_t arg2,
215 uint64_t arg3,
216 uint64_t arg4,
217 uint64_t arg5,
218 uint64_t arg6,
219 uint64_t arg7)
220{
Soby Mathewda43b662015-07-08 21:45:46 +0100221 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000222
Achin Guptabbc33f22014-05-09 13:33:42 +0100223 /*
224 * Save the time context and disable it to prevent the secure timer
225 * interrupt from interfering with wakeup from the suspend state.
226 */
227 tsp_generic_timer_save();
228 tsp_generic_timer_stop();
229
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000230 /* Update this cpu's statistics */
231 tsp_stats[linear_id].smc_count++;
232 tsp_stats[linear_id].eret_count++;
233 tsp_stats[linear_id].cpu_suspend_count++;
234
Dan Handley91b624e2014-07-29 17:14:00 +0100235#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000236 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000237 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
Soby Mathewda43b662015-07-08 21:45:46 +0100238 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100239 tsp_stats[linear_id].smc_count,
240 tsp_stats[linear_id].eret_count,
241 tsp_stats[linear_id].cpu_suspend_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000242 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100243#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000244
Achin Gupta607084e2014-02-09 18:24:19 +0000245 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000246 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
247}
248
249/*******************************************************************************
250 * This function performs any book keeping in the test secure payload after this
251 * cpu's architectural state has been restored after wakeup from an earlier psci
252 * cpu_suspend request.
253 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100254tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000255 uint64_t arg1,
256 uint64_t arg2,
257 uint64_t arg3,
258 uint64_t arg4,
259 uint64_t arg5,
260 uint64_t arg6,
261 uint64_t arg7)
262{
Soby Mathewda43b662015-07-08 21:45:46 +0100263 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000264
Achin Guptabbc33f22014-05-09 13:33:42 +0100265 /* Restore the generic timer context */
266 tsp_generic_timer_restore();
267
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000268 /* Update this cpu's statistics */
269 tsp_stats[linear_id].smc_count++;
270 tsp_stats[linear_id].eret_count++;
271 tsp_stats[linear_id].cpu_resume_count++;
272
Dan Handley91b624e2014-07-29 17:14:00 +0100273#if LOG_LEVEL >= LOG_LEVEL_INFO
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000274 spin_lock(&console_lock);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000275 INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n",
Soby Mathewda43b662015-07-08 21:45:46 +0100276 read_mpidr(), suspend_level);
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000277 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
Soby Mathewda43b662015-07-08 21:45:46 +0100278 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100279 tsp_stats[linear_id].smc_count,
280 tsp_stats[linear_id].eret_count,
281 tsp_stats[linear_id].cpu_suspend_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000282 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100283#endif
Achin Gupta607084e2014-02-09 18:24:19 +0000284 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000285 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
286}
287
288/*******************************************************************************
Juan Castillo4dc4a472014-08-12 11:17:06 +0100289 * This function performs any remaining bookkeeping in the test secure payload
290 * before the system is switched off (in response to a psci SYSTEM_OFF request)
291 ******************************************************************************/
292tsp_args_t *tsp_system_off_main(uint64_t arg0,
293 uint64_t arg1,
294 uint64_t arg2,
295 uint64_t arg3,
296 uint64_t arg4,
297 uint64_t arg5,
298 uint64_t arg6,
299 uint64_t arg7)
300{
Soby Mathewda43b662015-07-08 21:45:46 +0100301 uint32_t linear_id = plat_my_core_pos();
Juan Castillo4dc4a472014-08-12 11:17:06 +0100302
303 /* Update this cpu's statistics */
304 tsp_stats[linear_id].smc_count++;
305 tsp_stats[linear_id].eret_count++;
306
307#if LOG_LEVEL >= LOG_LEVEL_INFO
308 spin_lock(&console_lock);
Soby Mathewda43b662015-07-08 21:45:46 +0100309 INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
310 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
Juan Castillo4dc4a472014-08-12 11:17:06 +0100311 tsp_stats[linear_id].smc_count,
312 tsp_stats[linear_id].eret_count);
313 spin_unlock(&console_lock);
314#endif
315
316 /* Indicate to the SPD that we have completed this request */
317 return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
318}
319
320/*******************************************************************************
321 * This function performs any remaining bookkeeping in the test secure payload
322 * before the system is reset (in response to a psci SYSTEM_RESET request)
323 ******************************************************************************/
324tsp_args_t *tsp_system_reset_main(uint64_t arg0,
325 uint64_t arg1,
326 uint64_t arg2,
327 uint64_t arg3,
328 uint64_t arg4,
329 uint64_t arg5,
330 uint64_t arg6,
331 uint64_t arg7)
332{
Soby Mathewda43b662015-07-08 21:45:46 +0100333 uint32_t linear_id = plat_my_core_pos();
Juan Castillo4dc4a472014-08-12 11:17:06 +0100334
335 /* Update this cpu's statistics */
336 tsp_stats[linear_id].smc_count++;
337 tsp_stats[linear_id].eret_count++;
338
339#if LOG_LEVEL >= LOG_LEVEL_INFO
340 spin_lock(&console_lock);
Soby Mathewda43b662015-07-08 21:45:46 +0100341 INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
342 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
Juan Castillo4dc4a472014-08-12 11:17:06 +0100343 tsp_stats[linear_id].smc_count,
344 tsp_stats[linear_id].eret_count);
345 spin_unlock(&console_lock);
346#endif
347
348 /* Indicate to the SPD that we have completed this request */
349 return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0);
350}
351
352/*******************************************************************************
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000353 * TSP fast smc handler. The secure monitor jumps to this function by
354 * doing the ERET after populating X0-X7 registers. The arguments are received
355 * in the function arguments in order. Once the service is rendered, this
Soby Mathew9f71f702014-05-09 20:49:17 +0100356 * function returns to Secure Monitor by raising SMC.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000357 ******************************************************************************/
Soby Mathew9f71f702014-05-09 20:49:17 +0100358tsp_args_t *tsp_smc_handler(uint64_t func,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000359 uint64_t arg1,
360 uint64_t arg2,
361 uint64_t arg3,
362 uint64_t arg4,
363 uint64_t arg5,
364 uint64_t arg6,
365 uint64_t arg7)
366{
Achin Gupta916a2c12014-02-09 23:11:46 +0000367 uint64_t results[2];
368 uint64_t service_args[2];
Soby Mathewda43b662015-07-08 21:45:46 +0100369 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000370
Achin Gupta916a2c12014-02-09 23:11:46 +0000371 /* Update this cpu's statistics */
372 tsp_stats[linear_id].smc_count++;
373 tsp_stats[linear_id].eret_count++;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000374
Soby Mathewda43b662015-07-08 21:45:46 +0100375 INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100376 ((func >> 31) & 1) == 1 ? "fast" : "standard",
377 func);
Soby Mathewda43b662015-07-08 21:45:46 +0100378 INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100379 tsp_stats[linear_id].smc_count,
380 tsp_stats[linear_id].eret_count);
Achin Gupta916a2c12014-02-09 23:11:46 +0000381
382 /* Render secure services and obtain results here */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000383 results[0] = arg1;
384 results[1] = arg2;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000385
386 /*
387 * Request a service back from dispatcher/secure monitor. This call
388 * return and thereafter resume exectuion
389 */
390 tsp_get_magic(service_args);
391
392 /* Determine the function to perform based on the function ID */
Soby Mathew9f71f702014-05-09 20:49:17 +0100393 switch (TSP_BARE_FID(func)) {
394 case TSP_ADD:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000395 results[0] += service_args[0];
396 results[1] += service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000397 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100398 case TSP_SUB:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000399 results[0] -= service_args[0];
400 results[1] -= service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000401 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100402 case TSP_MUL:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000403 results[0] *= service_args[0];
404 results[1] *= service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000405 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100406 case TSP_DIV:
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000407 results[0] /= service_args[0] ? service_args[0] : 1;
408 results[1] /= service_args[1] ? service_args[1] : 1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000409 break;
410 default:
411 break;
412 }
413
Soby Mathew9f71f702014-05-09 20:49:17 +0100414 return set_smc_args(func, 0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000415 results[0],
416 results[1],
Soby Mathew9f71f702014-05-09 20:49:17 +0100417 0, 0, 0, 0);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000418}
419