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developerbeab2d72020-10-14 20:14:37 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
developer0e726372021-04-08 19:07:49 +08007#ifndef RTC_MT6359P_H
8#define RTC_MT6359P_H
developerbeab2d72020-10-14 20:14:37 +08009
10/* RTC registers */
11enum {
12 RTC_BBPU = 0x0588,
13 RTC_IRQ_STA = 0x058A,
14 RTC_IRQ_EN = 0x058C,
15 RTC_CII_EN = 0x058E
16};
17
18enum {
19 RTC_AL_SEC = 0x05A0,
20 RTC_AL_MIN = 0x05A2,
21 RTC_AL_HOU = 0x05A4,
22 RTC_AL_DOM = 0x05A6,
23 RTC_AL_DOW = 0x05A8,
24 RTC_AL_MTH = 0x05AA,
25 RTC_AL_YEA = 0x05AC,
26 RTC_AL_MASK = 0x0590
27};
28
29enum {
30 RTC_OSC32CON = 0x05AE,
31 RTC_CON = 0x05C4,
32 RTC_WRTGR = 0x05C2
33};
34
35enum {
36 RTC_POWERKEY1 = 0x05B0,
37 RTC_POWERKEY2 = 0x05B2
38};
39
40enum {
41 RTC_POWERKEY1_KEY = 0xA357,
42 RTC_POWERKEY2_KEY = 0x67D2
43};
44
45enum {
46 RTC_PDN1 = 0x05B4,
47 RTC_PDN2 = 0x05B6,
48 RTC_SPAR0 = 0x05B8,
49 RTC_SPAR1 = 0x05BA,
50 RTC_PROT = 0x05BC,
51 RTC_DIFF = 0x05BE,
52 RTC_CALI = 0x05C0
53};
54
55enum {
56 RTC_OSC32CON_UNLOCK1 = 0x1A57,
57 RTC_OSC32CON_UNLOCK2 = 0x2B68
58};
59
60enum {
61 RTC_LPD_EN = 0x0406,
62 RTC_LPD_RST = 0x040E
63};
64
65enum {
66 RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
67 RTC_LPD_OPT_EOSC_LPD = 1U << 13,
68 RTC_LPD_OPT_XOSC_LPD = 2U << 13,
69 RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
70};
71
72#define RTC_LPD_OPT_MASK (3U << 13)
73
74enum {
75 RTC_PROT_UNLOCK1 = 0x586A,
76 RTC_PROT_UNLOCK2 = 0x9136
77};
78
79enum {
80 RTC_BBPU_PWREN = 1U << 0,
81 RTC_BBPU_SPAR_SW = 1U << 1,
82 RTC_BBPU_RESET_SPAR = 1U << 2,
83 RTC_BBPU_RESET_ALARM = 1U << 3,
84 RTC_BBPU_CLRPKY = 1U << 4,
85 RTC_BBPU_RELOAD = 1U << 5,
86 RTC_BBPU_CBUSY = 1U << 6
87};
88
89enum {
90 RTC_AL_MASK_SEC = 1U << 0,
91 RTC_AL_MASK_MIN = 1U << 1,
92 RTC_AL_MASK_HOU = 1U << 2,
93 RTC_AL_MASK_DOM = 1U << 3,
94 RTC_AL_MASK_DOW = 1U << 4,
95 RTC_AL_MASK_MTH = 1U << 5,
96 RTC_AL_MASK_YEA = 1U << 6
97};
98
99enum {
100 RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
101 RTC_BBPU_2SEC_CK_SEL = 1U << 7,
102 RTC_BBPU_2SEC_EN = 1U << 8,
103 RTC_BBPU_2SEC_MODE = 0x3 << 9,
104 RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
105 RTC_BBPU_2SEC_STAT_STA = 1U << 12
106};
107
108enum {
109 RTC_BBPU_KEY = 0x43 << 8
110};
111
112enum {
113 RTC_EMBCK_SRC_SEL = 1 << 8,
114 RTC_EMBCK_SEL_MODE = 3 << 6,
115 RTC_XOSC32_ENB = 1 << 5,
116 RTC_REG_XOSC32_ENB = 1 << 15
117};
118
119enum {
120 RTC_K_EOSC_RSV_0 = 1 << 8,
121 RTC_K_EOSC_RSV_1 = 1 << 9,
122 RTC_K_EOSC_RSV_2 = 1 << 10
123};
124
125enum {
126 RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
127 RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
128 RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
129 RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
130 RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
131 RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
132};
133
134/* PMIC TOP Register Definition */
135enum {
136 PMIC_RG_TOP_CON = 0x0020,
137 PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
138 PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
139 PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
140 PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
141 PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
142 PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
143};
144
145/* PMIC SCK Register Definition */
146enum {
147 PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
148 PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
149 PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
150 PMIC_RG_EOSC_CALI_CON0 = 0x53A
151};
152
153enum {
154 PMIC_EOSC_CALI_START_ADDR = 0x53A
155};
156
157enum {
158 PMIC_EOSC_CALI_START_MASK = 0x1,
159 PMIC_EOSC_CALI_START_SHIFT = 0
160};
161
162/* PMIC DCXO Register Definition */
163enum {
164 PMIC_RG_DCXO_CW00 = 0x0788,
165 PMIC_RG_DCXO_CW02 = 0x0790,
166 PMIC_RG_DCXO_CW08 = 0x079C,
167 PMIC_RG_DCXO_CW09 = 0x079E,
168 PMIC_RG_DCXO_CW09_CLR = 0x07A2,
169 PMIC_RG_DCXO_CW10 = 0x07A4,
170 PMIC_RG_DCXO_CW12 = 0x07A8,
171 PMIC_RG_DCXO_CW13 = 0x07AA,
172 PMIC_RG_DCXO_CW15 = 0x07AE,
173 PMIC_RG_DCXO_CW19 = 0x07B6,
174};
175
176enum {
177 PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
178 PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
179 PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
180 PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
181 PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
182 PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
183 PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
184 PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
185 PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
186 PMIC_RG_XO_EN32K_MAN_SHIFT = 0
187};
188
189/* external API */
190uint16_t RTC_Read(uint32_t addr);
191void RTC_Write(uint32_t addr, uint16_t data);
192int32_t rtc_busy_wait(void);
193int32_t RTC_Write_Trigger(void);
194int32_t Writeif_unlock(void);
195void rtc_power_off_sequence(void);
196
developer0e726372021-04-08 19:07:49 +0800197#endif /* RTC_MT6359P_H */