fdts/tc3.dts

/*
 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>

#define LIT_CAPACITY			239
#define MID_CAPACITY			686
#define BIG_CAPACITY			1024

#define MHU_TX_ADDR			46040000 /* hex */
#define MHU_TX_COMPAT			"arm,mhuv3"
#define MHU_TX_INT_NAME			""

#define MHU_RX_ADDR			46140000 /* hex */
#define MHU_RX_COMPAT			"arm,mhuv3"
#define MHU_OFFSET			0x10000
#define MHU_MBOX_CELLS			3
#define MHU_RX_INT_NUM			300
#define MHU_RX_INT_NAME			"combined-mbx"

#define MPAM_ADDR			0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ			3750000

#if TARGET_FLAVOUR_FVP
#define DPU_ADDR			4000000000
#define DPU_IRQ				579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR			2cc00000
#define DPU_IRQ				69
#endif

#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"

/ {
	cpus {
		CPU2:cpu@200 {
			clocks = <&scmi_dvfs 1>;
			capacity-dmips-mhz = <MID_CAPACITY>;
		};

		CPU3:cpu@300 {
			clocks = <&scmi_dvfs 1>;
			capacity-dmips-mhz = <MID_CAPACITY>;
		};

		CPU6:cpu@600 {
			clocks = <&scmi_dvfs 2>;
			capacity-dmips-mhz = <BIG_CAPACITY>;
		};

		CPU7:cpu@700 {
			clocks = <&scmi_dvfs 2>;
			capacity-dmips-mhz = <BIG_CAPACITY>;
		};
	};

	cpu-pmu {
		interrupt-affinity = <&CPU0>,  <&CPU1>,  <&CPU2>,  <&CPU3>,
				     <&CPU4>,  <&CPU5>,  <&CPU6>,  <&CPU7>;
	};

	cs-pmu@0 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
	};

	cs-pmu@1 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
	};

	cs-pmu@2 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
	};

	cs-pmu@3 {
		compatible = "arm,coresight-pmu";
		reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
	};

	dsu-pmu {
		compatible = "arm,dsu-pmu";
		cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
	};

	sram: sram@6000000 {
		cpu_scp_scmi_p2a: scp-shmem@80 {
			compatible = "arm,scmi-shmem";
			reg = <0x80 0x80>;
		};
	};

	firmware {
		scmi {
			mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
			shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
		};
	};

#if TARGET_FLAVOUR_FVP
	smmu_700: iommu@3f000000 {
		status = "okay";
	};

	smmu_700_dpu: iommu@4002a00000 {
		status = "okay";
	};
#else
	smmu_600: smmu@2ce00000 {
		status = "okay";
	};
#endif

	dp0: display@DPU_ADDR {
#if TARGET_FLAVOUR_FVP
		iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
			 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
#else /* TARGET_FLAVOUR_FPGA */
		iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
			 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
			 <&smmu_600 8>, <&smmu_600 9>;
#endif
	};

	gpu: gpu@2d000000 {
#if TARGET_FLAVOUR_FVP
		iommus = <&smmu_700 0x200>;
#endif
	};
};