| Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| Varun Wadekar | 66ff012 | 2016-04-26 11:34:54 -0700 | [diff] [blame] | 33 | #include <common_def.h> |
| Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 34 | #include <memctrl_v2.h> |
| 35 | #include <tegra_def.h> |
| 36 | |
| 37 | #define TEGRA186_SMMU_CTX_SIZE 0x420 |
| 38 | |
| 39 | .align 4 |
| 40 | .globl tegra186_cpu_reset_handler |
| 41 | |
| 42 | /* CPU reset handler routine */ |
| 43 | func tegra186_cpu_reset_handler |
| 44 | /* |
| Varun Wadekar | 0a6eba3 | 2016-08-08 11:53:14 -0700 | [diff] [blame] | 45 | * The TZRAM loses state during System Suspend. We use this |
| 46 | * information to decide if the reset handler is running after a |
| 47 | * System Suspend. Resume from system suspend requires restoring |
| 48 | * the entire state from TZDRAM to TZRAM. |
| Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 49 | */ |
| Varun Wadekar | 0a6eba3 | 2016-08-08 11:53:14 -0700 | [diff] [blame] | 50 | mov x0, #BL31_BASE |
| 51 | ldr x0, [x0] |
| 52 | cbnz x0, boot_cpu |
| Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 53 | |
| 54 | /* resume from system suspend */ |
| 55 | mov x0, #BL31_BASE |
| 56 | adr x1, __tegra186_cpu_reset_handler_end |
| 57 | adr x2, __tegra186_cpu_reset_handler_data |
| 58 | ldr x2, [x2, #8] |
| 59 | |
| 60 | /* memcpy16 */ |
| 61 | m_loop16: |
| 62 | cmp x2, #16 |
| 63 | b.lt m_loop1 |
| 64 | ldp x3, x4, [x1], #16 |
| 65 | stp x3, x4, [x0], #16 |
| 66 | sub x2, x2, #16 |
| 67 | b m_loop16 |
| 68 | /* copy byte per byte */ |
| 69 | m_loop1: |
| 70 | cbz x2, boot_cpu |
| 71 | ldrb w3, [x1], #1 |
| 72 | strb w3, [x0], #1 |
| 73 | subs x2, x2, #1 |
| 74 | b.ne m_loop1 |
| 75 | |
| 76 | boot_cpu: |
| 77 | adr x0, __tegra186_cpu_reset_handler_data |
| 78 | ldr x0, [x0] |
| 79 | br x0 |
| 80 | endfunc tegra186_cpu_reset_handler |
| 81 | |
| 82 | /* |
| 83 | * Tegra186 reset data (offset 0x0 - 0x430) |
| 84 | * |
| 85 | * 0x000: secure world's entrypoint |
| 86 | * 0x008: BL31 size (RO + RW) |
| 87 | * 0x00C: SMMU context start |
| 88 | * 0x42C: SMMU context end |
| 89 | */ |
| 90 | |
| 91 | .align 4 |
| 92 | .type __tegra186_cpu_reset_handler_data, %object |
| 93 | .globl __tegra186_cpu_reset_handler_data |
| 94 | __tegra186_cpu_reset_handler_data: |
| 95 | .quad tegra_secure_entrypoint |
| 96 | .quad __BL31_END__ - BL31_BASE |
| 97 | .rept TEGRA186_SMMU_CTX_SIZE |
| 98 | .quad 0 |
| 99 | .endr |
| 100 | .size __tegra186_cpu_reset_handler_data, \ |
| 101 | . - __tegra186_cpu_reset_handler_data |
| 102 | |
| 103 | .align 4 |
| 104 | .globl __tegra186_cpu_reset_handler_end |
| 105 | __tegra186_cpu_reset_handler_end: |