blob: eefa62ff267fcc6630579ef7cbd4bc250e973131 [file] [log] [blame]
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02001/*
Biju Dasb99eb052020-12-13 20:24:19 +00002 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PWRC_H
8#define PWRC_H
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02009
10#define PPOFFR_OFF 0x0
11#define PPONR_OFF 0x4
12#define PCOFFR_OFF 0x8
13#define PWKUPR_OFF 0xc
14#define PSYSR_OFF 0x10
15
16#define PWKUPR_WEN (1ull << 31)
17
Justin Chadwelle454beb2019-07-03 14:11:06 +010018#define PSYSR_AFF_L2 (1U << 31)
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020019#define PSYSR_AFF_L1 (1 << 30)
20#define PSYSR_AFF_L0 (1 << 29)
21#define PSYSR_WEN (1 << 28)
22#define PSYSR_PC (1 << 27)
23#define PSYSR_PP (1 << 26)
24
25#define PSYSR_WK_SHIFT (24)
26#define PSYSR_WK_MASK (0x3)
27#define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK)
28
29#define WKUP_COLD 0x0
30#define WKUP_RESET 0x1
31#define WKUP_PPONR 0x2
32#define WKUP_GICREQ 0x3
33
Biju Dasb99eb052020-12-13 20:24:19 +000034#define RCAR_INVALID (0xffffffffU)
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020035#define PSYSR_INVALID 0xffffffff
36
Biju Dasb99eb052020-12-13 20:24:19 +000037#define RCAR_CLUSTER_A53A57 (0U)
38#define RCAR_CLUSTER_CA53 (1U)
39#define RCAR_CLUSTER_CA57 (2U)
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020040
Takuya Sakata0034f602021-11-02 20:30:02 +090041extern u_register_t rcar_boot_mpidr;
42
Julius Werner53456fc2019-07-09 13:49:11 -070043#ifndef __ASSEMBLER__
Takuya Sakata59197472021-11-02 20:30:39 +090044void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr);
45void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr);
Takuya Sakata0034f602021-11-02 20:30:02 +090046void rcar_pwrc_all_disable_interrupt_wakeup(void);
Takuya Sakata59197472021-11-02 20:30:39 +090047void rcar_pwrc_clusteroff(u_register_t mpidr);
48void rcar_pwrc_cpuoff(u_register_t mpidr);
49void rcar_pwrc_cpuon(u_register_t mpidr);
50int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020051void rcar_pwrc_setup(void);
52
Takuya Sakata59197472021-11-02 20:30:39 +090053uint32_t rcar_pwrc_get_cpu_wkr(u_register_t mpidr);
54uint32_t rcar_pwrc_status(u_register_t mpidr);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020055uint32_t rcar_pwrc_get_cluster(void);
Takuya Sakata59197472021-11-02 20:30:39 +090056uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020057uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
Toshiyuki Ogasaharab67a8ca2019-03-22 16:14:00 +090058void rcar_pwrc_restore_timer_state(void);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020059void plat_secondary_reset(void);
60
61void rcar_pwrc_code_copy_to_system_ram(void);
62
63#if !PMIC_ROHM_BD9571
64void rcar_pwrc_system_reset(void);
65#endif
66
67#if RCAR_SYSTEM_SUSPEND
68void rcar_pwrc_go_suspend_to_ram(void);
69void rcar_pwrc_set_suspend_to_ram(void);
70void rcar_pwrc_init_suspend_to_ram(void);
71void rcar_pwrc_suspend_to_ram(void);
72#endif
73
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020074extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack,
75 void *arg);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020076#endif
77
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000078#endif /* PWRC_H */