Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <arm_spm_def.h> |
| 10 | #include <assert.h> |
| 11 | #include <common_def.h> |
| 12 | #include <context.h> |
| 13 | #include <context_mgmt.h> |
| 14 | #include <debug.h> |
| 15 | #include <platform_def.h> |
| 16 | #include <platform.h> |
| 17 | #include <secure_partition.h> |
| 18 | #include <string.h> |
| 19 | #include <types.h> |
| 20 | #include <xlat_tables_v2.h> |
| 21 | |
| 22 | #include "spm_private.h" |
| 23 | #include "spm_shim_private.h" |
| 24 | |
| 25 | /* Allocate and initialise the translation context for the secure partition. */ |
| 26 | REGISTER_XLAT_CONTEXT2(secure_partition, |
| 27 | PLAT_SP_IMAGE_MMAP_REGIONS, |
| 28 | PLAT_SP_IMAGE_MAX_XLAT_TABLES, |
| 29 | PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE, |
| 30 | EL1_EL0_REGIME); |
| 31 | |
| 32 | /* Export a handle on the secure partition translation context */ |
| 33 | xlat_ctx_t *secure_partition_xlat_ctx_handle = &secure_partition_xlat_ctx; |
| 34 | |
| 35 | /* Setup context of the Secure Partition */ |
| 36 | void secure_partition_setup(void) |
| 37 | { |
| 38 | VERBOSE("S-EL1/S-EL0 context setup start...\n"); |
| 39 | |
| 40 | cpu_context_t *ctx = cm_get_context(SECURE); |
| 41 | |
| 42 | /* Make sure that we got a Secure context. */ |
| 43 | assert(ctx != NULL); |
| 44 | |
| 45 | /* Assert we are in Secure state. */ |
| 46 | assert((read_scr_el3() & SCR_NS_BIT) == 0); |
| 47 | |
| 48 | /* Disable MMU at EL1. */ |
| 49 | disable_mmu_icache_el1(); |
| 50 | |
| 51 | /* Invalidate TLBs at EL1. */ |
| 52 | tlbivmalle1(); |
| 53 | |
| 54 | /* |
| 55 | * General-Purpose registers |
| 56 | * ------------------------- |
| 57 | */ |
| 58 | |
| 59 | /* |
| 60 | * X0: Virtual address of a buffer shared between EL3 and Secure EL0. |
| 61 | * The buffer will be mapped in the Secure EL1 translation regime |
| 62 | * with Normal IS WBWA attributes and RO data and Execute Never |
| 63 | * instruction access permissions. |
| 64 | * |
| 65 | * X1: Size of the buffer in bytes |
| 66 | * |
| 67 | * X2: cookie value (Implementation Defined) |
| 68 | * |
| 69 | * X3: cookie value (Implementation Defined) |
| 70 | * |
| 71 | * X4 to X30 = 0 (already done by cm_init_my_context()) |
| 72 | */ |
| 73 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE); |
| 74 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, PLAT_SPM_BUF_SIZE); |
| 75 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, PLAT_SPM_COOKIE_0); |
| 76 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, PLAT_SPM_COOKIE_1); |
| 77 | |
| 78 | /* |
| 79 | * SP_EL0: A non-zero value will indicate to the SP that the SPM has |
| 80 | * initialized the stack pointer for the current CPU through |
| 81 | * implementation defined means. The value will be 0 otherwise. |
| 82 | */ |
| 83 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, |
| 84 | PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE); |
| 85 | |
| 86 | /* |
| 87 | * Setup translation tables |
| 88 | * ------------------------ |
| 89 | */ |
| 90 | |
| 91 | #if ENABLE_ASSERTIONS |
| 92 | |
| 93 | /* Get max granularity supported by the platform. */ |
| 94 | |
| 95 | u_register_t id_aa64prf0_el1 = read_id_aa64pfr0_el1(); |
| 96 | |
| 97 | int tgran64_supported = |
| 98 | ((id_aa64prf0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & |
| 99 | ID_AA64MMFR0_EL1_TGRAN64_MASK) == |
| 100 | ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; |
| 101 | |
| 102 | int tgran16_supported = |
| 103 | ((id_aa64prf0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & |
| 104 | ID_AA64MMFR0_EL1_TGRAN16_MASK) == |
| 105 | ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; |
| 106 | |
| 107 | int tgran4_supported = |
| 108 | ((id_aa64prf0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & |
| 109 | ID_AA64MMFR0_EL1_TGRAN4_MASK) == |
| 110 | ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; |
| 111 | |
| 112 | uintptr_t max_granule_size; |
| 113 | |
| 114 | if (tgran64_supported) { |
| 115 | max_granule_size = 64 * 1024; |
| 116 | } else if (tgran16_supported) { |
| 117 | max_granule_size = 16 * 1024; |
| 118 | } else { |
| 119 | assert(tgran4_supported); |
| 120 | max_granule_size = 4 * 1024; |
| 121 | } |
| 122 | |
| 123 | VERBOSE("Max translation granule supported: %lu KiB\n", |
| 124 | max_granule_size); |
| 125 | |
| 126 | uintptr_t max_granule_size_mask = max_granule_size - 1; |
| 127 | |
| 128 | /* Base must be aligned to the max granularity */ |
| 129 | assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_size_mask) == 0); |
| 130 | |
| 131 | /* Size must be a multiple of the max granularity */ |
| 132 | assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_size_mask) == 0); |
| 133 | |
| 134 | #endif /* ENABLE_ASSERTIONS */ |
| 135 | |
| 136 | /* This region contains the exception vectors used at S-EL1. */ |
| 137 | const mmap_region_t sel1_exception_vectors = |
| 138 | MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START, |
| 139 | SPM_SHIM_EXCEPTIONS_SIZE, |
| 140 | MT_CODE | MT_SECURE | MT_PRIVILEGED); |
| 141 | mmap_add_region_ctx(&secure_partition_xlat_ctx, |
| 142 | &sel1_exception_vectors); |
| 143 | |
| 144 | mmap_add_ctx(&secure_partition_xlat_ctx, |
| 145 | plat_get_secure_partition_mmap(NULL)); |
| 146 | |
| 147 | init_xlat_tables_ctx(&secure_partition_xlat_ctx); |
| 148 | |
| 149 | /* |
| 150 | * MMU-related registers |
| 151 | * --------------------- |
| 152 | */ |
| 153 | |
| 154 | /* Set attributes in the right indices of the MAIR */ |
| 155 | u_register_t mair_el1 = |
| 156 | MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX) | |
| 157 | MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX) | |
| 158 | MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); |
| 159 | |
| 160 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, mair_el1); |
| 161 | |
| 162 | /* Setup TCR_EL1. */ |
| 163 | u_register_t tcr_ps_bits = tcr_physical_addr_size_bits(PLAT_PHY_ADDR_SPACE_SIZE); |
| 164 | |
| 165 | u_register_t tcr_el1 = |
| 166 | /* Size of region addressed by TTBR0_EL1 = 2^(64-T0SZ) bytes. */ |
| 167 | (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE)) | |
| 168 | /* Inner and outer WBWA, shareable. */ |
| 169 | TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | |
| 170 | /* Set the granularity to 4KB. */ |
| 171 | TCR_TG0_4K | |
| 172 | /* Limit Intermediate Physical Address Size. */ |
| 173 | tcr_ps_bits << TCR_EL1_IPS_SHIFT | |
| 174 | /* Disable translations using TBBR1_EL1. */ |
| 175 | TCR_EPD1_BIT |
| 176 | /* The remaining fields related to TBBR1_EL1 are left as zero. */ |
| 177 | ; |
| 178 | |
| 179 | tcr_el1 &= ~( |
| 180 | /* Enable translations using TBBR0_EL1 */ |
| 181 | TCR_EPD0_BIT |
| 182 | ); |
| 183 | |
| 184 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, tcr_el1); |
| 185 | |
| 186 | /* Setup SCTLR_EL1 */ |
| 187 | u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); |
| 188 | |
| 189 | sctlr_el1 |= |
| 190 | /*SCTLR_EL1_RES1 |*/ |
| 191 | /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ |
| 192 | SCTLR_UCI_BIT | |
| 193 | /* RW regions at xlat regime EL1&0 are forced to be XN. */ |
| 194 | SCTLR_WXN_BIT | |
| 195 | /* Don't trap to EL1 execution of WFI or WFE at EL0. */ |
| 196 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | |
| 197 | /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ |
| 198 | SCTLR_UCT_BIT | |
| 199 | /* Don't trap to EL1 execution of DZ ZVA at EL0. */ |
| 200 | SCTLR_DZE_BIT | |
| 201 | /* Enable SP Alignment check for EL0 */ |
| 202 | SCTLR_SA0_BIT | |
| 203 | /* Allow cacheable data and instr. accesses to normal memory. */ |
| 204 | SCTLR_C_BIT | SCTLR_I_BIT | |
| 205 | /* Alignment fault checking enabled when at EL1 and EL0. */ |
| 206 | SCTLR_A_BIT | |
| 207 | /* Enable MMU. */ |
| 208 | SCTLR_M_BIT |
| 209 | ; |
| 210 | |
| 211 | sctlr_el1 &= ~( |
| 212 | /* Explicit data accesses at EL0 are little-endian. */ |
| 213 | SCTLR_E0E_BIT | |
| 214 | /* Accesses to DAIF from EL0 are trapped to EL1. */ |
| 215 | SCTLR_UMA_BIT |
| 216 | ); |
| 217 | |
| 218 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); |
| 219 | |
| 220 | /* Point TTBR0_EL1 at the tables of the context created for the SP. */ |
| 221 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, |
| 222 | (u_register_t)secure_partition_base_xlat_table); |
| 223 | |
| 224 | /* |
| 225 | * Setup other system registers |
| 226 | * ---------------------------- |
| 227 | */ |
| 228 | |
| 229 | /* Shim Exception Vector Base Address */ |
| 230 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, |
| 231 | SPM_SHIM_EXCEPTIONS_PTR); |
| 232 | |
| 233 | /* |
| 234 | * FPEN: Forbid the Secure Partition to access FP/SIMD registers. |
| 235 | * TTA: Enable access to trace registers. |
| 236 | * ZEN (v8.2): Trap SVE instructions and access to SVE registers. |
| 237 | */ |
| 238 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, |
| 239 | CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_ALL)); |
| 240 | |
| 241 | /* |
| 242 | * Prepare information in buffer shared between EL3 and S-EL0 |
| 243 | * ---------------------------------------------------------- |
| 244 | */ |
| 245 | |
| 246 | void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE; |
| 247 | |
| 248 | /* Copy the boot information into the shared buffer with the SP. */ |
| 249 | assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t) |
| 250 | <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)); |
| 251 | |
| 252 | assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1)); |
| 253 | |
| 254 | const secure_partition_boot_info_t *sp_boot_info = |
| 255 | plat_get_secure_partition_boot_info(NULL); |
| 256 | |
| 257 | assert(sp_boot_info != NULL); |
| 258 | |
| 259 | memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info, |
| 260 | sizeof(secure_partition_boot_info_t)); |
| 261 | |
| 262 | /* Pointer to the MP information from the platform port. */ |
| 263 | secure_partition_mp_info_t *sp_mp_info = |
| 264 | ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info; |
| 265 | |
| 266 | assert(sp_mp_info != NULL); |
| 267 | |
| 268 | /* |
| 269 | * Point the shared buffer MP information pointer to where the info will |
| 270 | * be populated, just after the boot info. |
| 271 | */ |
| 272 | ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info = |
| 273 | ((secure_partition_mp_info_t *) shared_buf_ptr) + |
| 274 | sizeof(secure_partition_boot_info_t); |
| 275 | |
| 276 | /* |
| 277 | * Update the shared buffer pointer to where the MP information for the |
| 278 | * payload will be populated |
| 279 | */ |
| 280 | shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info; |
| 281 | |
| 282 | /* |
| 283 | * Copy the cpu information into the shared buffer area after the boot |
| 284 | * information. |
| 285 | */ |
| 286 | assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT); |
| 287 | |
| 288 | assert((uintptr_t)shared_buf_ptr |
| 289 | <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE - |
| 290 | (sp_boot_info->num_cpus * sizeof(*sp_mp_info)))); |
| 291 | |
| 292 | memcpy(shared_buf_ptr, (const void *) sp_mp_info, |
| 293 | sp_boot_info->num_cpus * sizeof(*sp_mp_info)); |
| 294 | |
| 295 | /* |
| 296 | * Calculate the linear indices of cores in boot information for the |
| 297 | * secure partition and flag the primary CPU |
| 298 | */ |
| 299 | sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr; |
| 300 | |
| 301 | for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) { |
| 302 | u_register_t mpidr = sp_mp_info[index].mpidr; |
| 303 | |
| 304 | sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr); |
| 305 | if (plat_my_core_pos() == sp_mp_info[index].linear_id) |
| 306 | sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU; |
| 307 | } |
| 308 | |
| 309 | VERBOSE("S-EL1/S-EL0 context setup end.\n"); |
| 310 | } |