Leo Yan | b4d7134 | 2024-04-14 08:27:39 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | /dts-v1/; |
| 7 | |
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9 | #include <dt-bindings/interrupt-controller/irq.h> |
| 10 | #include <platform_def.h> |
| 11 | |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 12 | #if TARGET_FLAVOUR_FVP |
| 13 | #define LIT_CAPACITY 406 |
| 14 | #define MID_CAPACITY 912 |
| 15 | #else /* TARGET_FLAVOUR_FPGA */ |
| 16 | #define LIT_CAPACITY 280 |
| 17 | #define MID_CAPACITY 775 |
| 18 | /* this is an area optimized configuration of the big core */ |
| 19 | #define BIG2_CAPACITY 930 |
| 20 | #endif /* TARGET_FLAVOUR_FPGA */ |
| 21 | #define BIG_CAPACITY 1024 |
| 22 | |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 23 | #define MHU_TX_ADDR 45000000 /* hex */ |
Boyan Karatotev | cd2b4cc | 2024-04-24 10:09:18 +0100 | [diff] [blame] | 24 | #define MHU_TX_COMPAT "arm,mhuv2-tx","arm,primecell" |
| 25 | #define MHU_TX_INT_NAME "mhu_tx" |
| 26 | |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 27 | #define MHU_RX_ADDR 45010000 /* hex */ |
Boyan Karatotev | cd2b4cc | 2024-04-24 10:09:18 +0100 | [diff] [blame] | 28 | #define MHU_RX_COMPAT "arm,mhuv2-rx","arm,primecell" |
| 29 | #define MHU_OFFSET 0x1000 |
| 30 | #define MHU_MBOX_CELLS 2 |
| 31 | #define MHU_RX_INT_NUM 317 |
| 32 | #define MHU_RX_INT_NAME "mhu_rx" |
| 33 | |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 34 | #define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ |
| 35 | #define UARTCLK_FREQ 5000000 |
| 36 | |
| 37 | #define DPU_ADDR 2cc00000 |
| 38 | #define DPU_IRQ 69 |
| 39 | |
Leo Yan | b4d7134 | 2024-04-14 08:27:39 +0100 | [diff] [blame] | 40 | #include "tc-common.dtsi" |
| 41 | #if TARGET_FLAVOUR_FVP |
| 42 | #include "tc-fvp.dtsi" |
Leo Yan | 815f550 | 2024-04-24 09:57:28 +0100 | [diff] [blame] | 43 | #else |
| 44 | #include "tc-fpga.dtsi" |
Leo Yan | b4d7134 | 2024-04-14 08:27:39 +0100 | [diff] [blame] | 45 | #endif /* TARGET_FLAVOUR_FVP */ |
| 46 | #include "tc-base.dtsi" |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 47 | |
| 48 | / { |
Leo Yan | 6705ff0 | 2024-04-14 22:09:34 +0100 | [diff] [blame] | 49 | cpus { |
| 50 | #if TARGET_FLAVOUR_FPGA |
| 51 | cpu-map { |
| 52 | cluster0 { |
| 53 | core8 { |
| 54 | cpu = <&CPU8>; |
| 55 | }; |
| 56 | core9 { |
| 57 | cpu = <&CPU9>; |
| 58 | }; |
| 59 | core10 { |
| 60 | cpu = <&CPU10>; |
| 61 | }; |
| 62 | core11 { |
| 63 | cpu = <&CPU11>; |
| 64 | }; |
| 65 | core12 { |
| 66 | cpu = <&CPU12>; |
| 67 | }; |
| 68 | core13 { |
| 69 | cpu = <&CPU13>; |
| 70 | }; |
| 71 | }; |
| 72 | }; |
| 73 | #endif |
| 74 | |
| 75 | CPU2:cpu@200 { |
| 76 | clocks = <&scmi_dvfs 0>; |
| 77 | capacity-dmips-mhz = <LIT_CAPACITY>; |
| 78 | }; |
| 79 | |
| 80 | CPU3:cpu@300 { |
| 81 | clocks = <&scmi_dvfs 0>; |
| 82 | capacity-dmips-mhz = <LIT_CAPACITY>; |
| 83 | }; |
| 84 | |
| 85 | CPU6:cpu@600 { |
| 86 | clocks = <&scmi_dvfs 1>; |
| 87 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 88 | }; |
| 89 | |
| 90 | CPU7:cpu@700 { |
| 91 | clocks = <&scmi_dvfs 1>; |
| 92 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 93 | }; |
| 94 | |
| 95 | #if TARGET_FLAVOUR_FPGA |
| 96 | CPU8:cpu@800 { |
| 97 | device_type = "cpu"; |
| 98 | compatible = "arm,armv8"; |
| 99 | reg = <0x800>; |
| 100 | enable-method = "psci"; |
| 101 | clocks = <&scmi_dvfs 1>; |
| 102 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 103 | amu = <&amu>; |
| 104 | supports-mpmm; |
| 105 | }; |
| 106 | |
| 107 | CPU9:cpu@900 { |
| 108 | device_type = "cpu"; |
| 109 | compatible = "arm,armv8"; |
| 110 | reg = <0x900>; |
| 111 | enable-method = "psci"; |
| 112 | clocks = <&scmi_dvfs 2>; |
| 113 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 114 | amu = <&amu>; |
| 115 | supports-mpmm; |
| 116 | }; |
| 117 | |
| 118 | CPU10:cpu@A00 { |
| 119 | device_type = "cpu"; |
| 120 | compatible = "arm,armv8"; |
| 121 | reg = <0xA00>; |
| 122 | enable-method = "psci"; |
| 123 | clocks = <&scmi_dvfs 2>; |
| 124 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 125 | amu = <&amu>; |
| 126 | supports-mpmm; |
| 127 | }; |
| 128 | |
| 129 | CPU11:cpu@B00 { |
| 130 | device_type = "cpu"; |
| 131 | compatible = "arm,armv8"; |
| 132 | reg = <0xB00>; |
| 133 | enable-method = "psci"; |
| 134 | clocks = <&scmi_dvfs 2>; |
| 135 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 136 | amu = <&amu>; |
| 137 | supports-mpmm; |
| 138 | }; |
| 139 | |
| 140 | CPU12:cpu@C00 { |
| 141 | device_type = "cpu"; |
| 142 | compatible = "arm,armv8"; |
| 143 | reg = <0xC00>; |
| 144 | enable-method = "psci"; |
| 145 | clocks = <&scmi_dvfs 3>; |
| 146 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 147 | amu = <&amu>; |
| 148 | supports-mpmm; |
| 149 | }; |
| 150 | |
| 151 | CPU13:cpu@D00 { |
| 152 | device_type = "cpu"; |
| 153 | compatible = "arm,armv8"; |
| 154 | reg = <0xD00>; |
| 155 | enable-method = "psci"; |
| 156 | clocks = <&scmi_dvfs 3>; |
| 157 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 158 | amu = <&amu>; |
| 159 | supports-mpmm; |
| 160 | }; |
| 161 | #endif |
| 162 | }; |
| 163 | |
| 164 | #if TARGET_FLAVOUR_FPGA |
| 165 | ete8 { |
| 166 | compatible = "arm,embedded-trace-extension"; |
| 167 | cpu = <&CPU8>; |
| 168 | }; |
| 169 | |
| 170 | ete9 { |
| 171 | compatible = "arm,embedded-trace-extension"; |
| 172 | cpu = <&CPU9>; |
| 173 | }; |
| 174 | |
| 175 | ete10 { |
| 176 | compatible = "arm,embedded-trace-extension"; |
| 177 | cpu = <&CPU10>; |
| 178 | }; |
| 179 | |
| 180 | ete11 { |
| 181 | compatible = "arm,embedded-trace-extension"; |
| 182 | cpu = <&CPU11>; |
| 183 | }; |
| 184 | |
| 185 | ete12 { |
| 186 | compatible = "arm,embedded-trace-extension"; |
| 187 | cpu = <&CPU12>; |
| 188 | }; |
| 189 | |
| 190 | ete13 { |
| 191 | compatible = "arm,embedded-trace-extension"; |
| 192 | cpu = <&CPU13>; |
| 193 | }; |
| 194 | #endif /* TARGET_FLAVOUR_FPGA */ |
| 195 | |
| 196 | cpu-pmu { |
| 197 | #if TARGET_FLAVOUR_FPGA |
| 198 | interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, |
| 199 | <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, |
| 200 | <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, |
| 201 | <&CPU12>, <&CPU13>; |
| 202 | #else |
| 203 | interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, |
| 204 | <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; |
| 205 | #endif |
| 206 | }; |
| 207 | |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 208 | cmn-pmu { |
| 209 | compatible = "arm,ci-700"; |
| 210 | reg = <0x0 0x50000000 0x0 0x10000000>; |
| 211 | interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; |
| 212 | }; |
Leo Yan | 6705ff0 | 2024-04-14 22:09:34 +0100 | [diff] [blame] | 213 | |
Boyan Karatotev | d1f5550 | 2024-04-19 12:00:49 +0100 | [diff] [blame] | 214 | mbox_db_rx: mhu@MHU_RX_ADDR { |
| 215 | arm,mhuv2-protocols = <0 1>; |
| 216 | }; |
| 217 | |
| 218 | mbox_db_tx: mhu@MHU_TX_ADDR { |
| 219 | arm,mhuv2-protocols = <0 1>; |
| 220 | }; |
| 221 | |
Boyan Karatotev | 102554c | 2024-04-19 12:27:46 +0100 | [diff] [blame] | 222 | firmware { |
| 223 | /* |
| 224 | * TC2 does not have a P2A channel, but wiring one was needed to make Linux work |
| 225 | * (by chance). At the time the SCMI driver did not support bidirectional |
| 226 | * mailboxes so as a workaround, the A2P channel was wired for TX communication |
| 227 | * and the synchronous replies would be read asyncrhonously as if coming from |
| 228 | * the P2A channel, while being the actual A2P channel. |
| 229 | * |
| 230 | * This will not work with kernels > 5.15, but keep it around to keep TC2 |
| 231 | * working with its target kernel. Newer kernels will still work, but SCMI |
| 232 | * won't as they check that the two regions are distinct. |
| 233 | */ |
| 234 | scmi { |
| 235 | mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>; |
| 236 | shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>; |
| 237 | }; |
| 238 | }; |
| 239 | |
Leo Yan | 983fd45 | 2024-06-04 12:51:12 +0100 | [diff] [blame] | 240 | smmu_700: iommu@3f000000 { |
| 241 | status = "okay"; |
| 242 | }; |
| 243 | |
Leo Yan | 6705ff0 | 2024-04-14 22:09:34 +0100 | [diff] [blame] | 244 | dp0: display@DPU_ADDR { |
| 245 | #if TC_SCMI_PD_CTRL_EN |
| 246 | power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>; |
| 247 | #endif |
Leo Yan | 983fd45 | 2024-06-04 12:51:12 +0100 | [diff] [blame] | 248 | iommus = <&smmu_700 0x100>; |
| 249 | }; |
| 250 | |
| 251 | gpu: gpu@2d000000 { |
| 252 | iommus = <&smmu_700 0x200>; |
Leo Yan | 6705ff0 | 2024-04-14 22:09:34 +0100 | [diff] [blame] | 253 | }; |
Leo Yan | 4d4a197 | 2024-04-24 09:53:21 +0100 | [diff] [blame] | 254 | }; |