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Sandrine Bailleux798140d2014-07-17 16:06:39 +01001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Juan Castillob3286c02014-10-20 12:29:58 +010032#include <arm_gic.h>
Sandrine Bailleux798140d2014-07-17 16:06:39 +010033#include <assert.h>
34#include <bl31.h>
35#include <bl_common.h>
36#include <cci400.h>
37#include <console.h>
38#include <mmio.h>
39#include <platform.h>
40#include <stddef.h>
41#include "juno_def.h"
42#include "juno_private.h"
43#include "mhu.h"
44
45/*******************************************************************************
46 * Declarations of linker defined symbols which will help us find the layout
47 * of trusted RAM
48 ******************************************************************************/
49extern unsigned long __RO_START__;
50extern unsigned long __RO_END__;
Soby Mathew2ae20432015-01-08 18:02:44 +000051extern unsigned long __BL31_END__;
Sandrine Bailleux798140d2014-07-17 16:06:39 +010052
Soby Mathew2ae20432015-01-08 18:02:44 +000053#if USE_COHERENT_MEM
Sandrine Bailleux798140d2014-07-17 16:06:39 +010054extern unsigned long __COHERENT_RAM_START__;
55extern unsigned long __COHERENT_RAM_END__;
Soby Mathew2ae20432015-01-08 18:02:44 +000056#endif
Sandrine Bailleux798140d2014-07-17 16:06:39 +010057
58/*
Soby Mathew2ae20432015-01-08 18:02:44 +000059 * The next 3 constants identify the extents of the code, RO data region and the
60 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
61 * therefore they must be page-aligned. It is the responsibility of the linker
62 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
63 * refer to page-aligned addresses.
Sandrine Bailleux798140d2014-07-17 16:06:39 +010064 */
65#define BL31_RO_BASE (unsigned long)(&__RO_START__)
66#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
Soby Mathew2ae20432015-01-08 18:02:44 +000067#define BL31_END (unsigned long)(&__BL31_END__)
Sandrine Bailleux798140d2014-07-17 16:06:39 +010068
Soby Mathew2ae20432015-01-08 18:02:44 +000069#if USE_COHERENT_MEM
Sandrine Bailleux798140d2014-07-17 16:06:39 +010070/*
71 * The next 2 constants identify the extents of the coherent memory region.
72 * These addresses are used by the MMU setup code and therefore they must be
73 * page-aligned. It is the responsibility of the linker script to ensure that
74 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
75 * refer to page-aligned addresses.
76 */
77#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
78#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Soby Mathew2ae20432015-01-08 18:02:44 +000079#endif
Sandrine Bailleux798140d2014-07-17 16:06:39 +010080
81/******************************************************************************
82 * Placeholder variables for copying the arguments that have been passed to
83 * BL3-1 from BL2.
84 ******************************************************************************/
85static entry_point_info_t bl32_ep_info;
86static entry_point_info_t bl33_ep_info;
87
88/*******************************************************************************
89 * Return a pointer to the 'entry_point_info' structure of the next image for
90 * the security state specified. BL3-3 corresponds to the non-secure image type
91 * while BL3-2 corresponds to the secure image type. A NULL pointer is returned
92 * if the image does not exist.
93 ******************************************************************************/
94entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
95{
96 entry_point_info_t *next_image_info;
97
98 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
99
100 /* None of the images on this platform can have 0x0 as the entrypoint */
101 if (next_image_info->pc)
102 return next_image_info;
103 else
104 return NULL;
105}
106
107/*******************************************************************************
108 * Perform any BL3-1 specific platform actions. Here is an opportunity to copy
109 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
110 * are lost (potentially). This needs to be done before the MMU is initialized
111 * so that the memory layout can be used while creating page tables. Also, BL2
112 * has flushed this information to memory, so we are guaranteed to pick up good
113 * data
114 ******************************************************************************/
115void bl31_early_platform_setup(bl31_params_t *from_bl2,
116 void *plat_params_from_bl2)
117{
118 /* Initialize the console to provide early debug support */
Soby Mathewf797cea2014-08-21 15:20:27 +0100119 console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100120
121 /*
122 * Initialise the CCI-400 driver for BL31 so that it is accessible after
123 * a warm boot. BL1 should have already enabled CCI coherency for this
124 * cluster during cold boot.
125 */
126 cci_init(CCI400_BASE,
127 CCI400_SL_IFACE3_CLUSTER_IX,
128 CCI400_SL_IFACE4_CLUSTER_IX);
129
130 /*
131 * Check params passed from BL2 should not be NULL,
132 */
133 assert(from_bl2 != NULL);
134 assert(from_bl2->h.type == PARAM_BL31);
135 assert(from_bl2->h.version >= VERSION_1);
136 /*
137 * In debug builds, we pass a special value in 'plat_params_from_bl2'
138 * to verify platform parameters from BL2 to BL3-1.
139 * In release builds, it's not used.
140 */
141 assert(((unsigned long long)plat_params_from_bl2) ==
142 JUNO_BL31_PLAT_PARAM_VAL);
143
144 /*
145 * Copy BL3-2 and BL3-3 entry point information.
146 * They are stored in Secure RAM, in BL2's address space.
147 */
148 bl32_ep_info = *from_bl2->bl32_ep_info;
149 bl33_ep_info = *from_bl2->bl33_ep_info;
150}
151
152/*******************************************************************************
153 * Initialize the MHU and the GIC.
154 ******************************************************************************/
155void bl31_platform_setup(void)
156{
157 unsigned int reg_val;
158
159 mhu_secure_init();
160
161 /* Initialize the gic cpu and distributor interfaces */
Juan Castillob3286c02014-10-20 12:29:58 +0100162 plat_gic_init();
163 arm_gic_setup();
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100164
165 /* Enable and initialize the System level generic timer */
166 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
167
168 /* Allow access to the System counter timer module */
169 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
170 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
171 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
172 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
173
174 reg_val = (1 << CNTNSAR_NS_SHIFT(1));
175 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
176
177 /* Topologies are best known to the platform. */
178 plat_setup_topology();
179}
180
181/*******************************************************************************
182 * Perform the very early platform specific architectural setup here. At the
183 * moment this is only intializes the mmu in a quick and dirty way.
184 ******************************************************************************/
185void bl31_plat_arch_setup()
186{
187 configure_mmu_el3(BL31_RO_BASE,
Soby Mathew2ae20432015-01-08 18:02:44 +0000188 (BL31_END - BL31_RO_BASE),
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100189 BL31_RO_BASE,
Soby Mathew2ae20432015-01-08 18:02:44 +0000190 BL31_RO_LIMIT
191#if USE_COHERENT_MEM
192 ,
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100193 BL31_COHERENT_RAM_BASE,
Soby Mathew2ae20432015-01-08 18:02:44 +0000194 BL31_COHERENT_RAM_LIMIT
195#endif
196 );
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100197}