Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __MCE_H__ |
| 32 | #define __MCE_H__ |
| 33 | |
| 34 | #include <mmio.h> |
| 35 | #include <tegra_def.h> |
| 36 | |
| 37 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 38 | * MCE commands |
| 39 | ******************************************************************************/ |
| 40 | typedef enum mce_cmd { |
| 41 | MCE_CMD_ENTER_CSTATE = 0, |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 42 | MCE_CMD_UPDATE_CSTATE_INFO = 1, |
| 43 | MCE_CMD_UPDATE_CROSSOVER_TIME = 2, |
| 44 | MCE_CMD_READ_CSTATE_STATS = 3, |
| 45 | MCE_CMD_WRITE_CSTATE_STATS = 4, |
| 46 | MCE_CMD_IS_SC7_ALLOWED = 5, |
| 47 | MCE_CMD_ONLINE_CORE = 6, |
| 48 | MCE_CMD_CC3_CTRL = 7, |
| 49 | MCE_CMD_ECHO_DATA = 8, |
| 50 | MCE_CMD_READ_VERSIONS = 9, |
| 51 | MCE_CMD_ENUM_FEATURES = 10, |
| 52 | MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11, |
| 53 | MCE_CMD_ENUM_READ_MCA = 12, |
| 54 | MCE_CMD_ENUM_WRITE_MCA = 13, |
| 55 | MCE_CMD_ROC_FLUSH_CACHE = 14, |
| 56 | MCE_CMD_ROC_CLEAN_CACHE = 15, |
| 57 | MCE_CMD_ENABLE_LATIC = 16, |
| 58 | MCE_CMD_UNCORE_PERFMON_REQ = 17, |
| 59 | MCE_CMD_MISC_CCPLEX = 18, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 60 | MCE_CMD_IS_CCX_ALLOWED = 0xFE, |
| 61 | MCE_CMD_MAX = 0xFF, |
| 62 | } mce_cmd_t; |
| 63 | |
| 64 | #define MCE_CMD_MASK 0xFF |
| 65 | |
| 66 | /******************************************************************************* |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 67 | * Struct to prepare UPDATE_CSTATE_INFO request |
| 68 | ******************************************************************************/ |
| 69 | typedef struct mce_cstate_info { |
| 70 | /* cluster cstate value */ |
| 71 | uint32_t cluster; |
| 72 | /* ccplex cstate value */ |
| 73 | uint32_t ccplex; |
| 74 | /* system cstate value */ |
| 75 | uint32_t system; |
| 76 | /* force system state? */ |
| 77 | uint8_t system_state_force; |
| 78 | /* wake mask value */ |
| 79 | uint32_t wake_mask; |
| 80 | /* update the wake mask? */ |
| 81 | uint8_t update_wake_mask; |
| 82 | } mce_cstate_info_t; |
| 83 | |
| 84 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 85 | * Macros to prepare CSTATE info request |
| 86 | ******************************************************************************/ |
| 87 | /* Description of the parameters for UPDATE_CSTATE_INFO request */ |
| 88 | #define CLUSTER_CSTATE_MASK 0x7 |
| 89 | #define CLUSTER_CSTATE_SHIFT 0 |
| 90 | #define CLUSTER_CSTATE_UPDATE_BIT (1 << 7) |
| 91 | #define CCPLEX_CSTATE_MASK 0x3 |
| 92 | #define CCPLEX_CSTATE_SHIFT 8 |
| 93 | #define CCPLEX_CSTATE_UPDATE_BIT (1 << 15) |
| 94 | #define SYSTEM_CSTATE_MASK 0xF |
| 95 | #define SYSTEM_CSTATE_SHIFT 16 |
| 96 | #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22 |
| 97 | #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22) |
| 98 | #define SYSTEM_CSTATE_UPDATE_BIT (1 << 23) |
| 99 | #define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31) |
| 100 | #define CSTATE_WAKE_MASK_SHIFT 32 |
| 101 | #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF |
| 102 | |
| 103 | /******************************************************************************* |
| 104 | * Auto-CC3 control macros |
| 105 | ******************************************************************************/ |
| 106 | #define MCE_AUTO_CC3_FREQ_MASK 0x1FF |
| 107 | #define MCE_AUTO_CC3_FREQ_SHIFT 0 |
| 108 | #define MCE_AUTO_CC3_VTG_MASK 0x7F |
| 109 | #define MCE_AUTO_CC3_VTG_SHIFT 16 |
| 110 | #define MCE_AUTO_CC3_ENABLE_BIT (1 << 31) |
| 111 | |
| 112 | /******************************************************************************* |
| 113 | * Macros for the 'IS_SC7_ALLOWED' command |
| 114 | ******************************************************************************/ |
| 115 | #define MCE_SC7_ALLOWED_MASK 0x7 |
| 116 | #define MCE_SC7_WAKE_TIME_SHIFT 32 |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * Macros for 'read/write ctats' commands |
| 120 | ******************************************************************************/ |
| 121 | #define MCE_CSTATE_STATS_TYPE_SHIFT 32 |
| 122 | #define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF |
| 123 | |
| 124 | /******************************************************************************* |
| 125 | * Macros for 'update crossover threshold' command |
| 126 | ******************************************************************************/ |
| 127 | #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32 |
| 128 | |
| 129 | /******************************************************************************* |
| 130 | * Timeout value used to powerdown a core |
| 131 | ******************************************************************************/ |
| 132 | #define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF |
| 133 | |
| 134 | /******************************************************************************* |
| 135 | * MCA command struct |
| 136 | ******************************************************************************/ |
| 137 | typedef union mca_cmd { |
| 138 | struct command { |
| 139 | uint8_t cmd; |
| 140 | uint8_t idx; |
| 141 | uint8_t subidx; |
| 142 | } command; |
| 143 | struct input { |
| 144 | uint32_t low; |
| 145 | uint32_t high; |
| 146 | } input; |
| 147 | uint64_t data; |
| 148 | } mca_cmd_t; |
| 149 | |
| 150 | /******************************************************************************* |
| 151 | * MCA argument struct |
| 152 | ******************************************************************************/ |
| 153 | typedef union mca_arg { |
| 154 | struct err { |
| 155 | uint64_t error:8; |
| 156 | uint64_t unused:48; |
| 157 | uint64_t finish:8; |
| 158 | } err; |
| 159 | struct arg { |
| 160 | uint32_t low; |
| 161 | uint32_t high; |
| 162 | } arg; |
| 163 | uint64_t data; |
| 164 | } mca_arg_t; |
| 165 | |
| 166 | /******************************************************************************* |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 167 | * Uncore PERFMON ARI struct |
| 168 | ******************************************************************************/ |
| 169 | typedef union uncore_perfmon_req { |
| 170 | struct perfmon_command { |
| 171 | /* |
| 172 | * Commands: 0 = READ, 1 = WRITE |
| 173 | */ |
| 174 | uint64_t cmd:8; |
| 175 | /* |
| 176 | * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 |
| 177 | */ |
| 178 | uint64_t grp:4; |
| 179 | /* |
| 180 | * Unit selector: Selects the unit instance, with 0 = Unit |
| 181 | * = (number of units in group) - 1. |
| 182 | */ |
| 183 | uint64_t unit:4; |
| 184 | /* |
| 185 | * Selects the uncore perfmon register to access |
| 186 | */ |
| 187 | uint64_t reg:8; |
| 188 | /* |
| 189 | * Counter number. Selects which counter to use for |
| 190 | * registers NV_PMEVCNTR and NV_PMEVTYPER. |
| 191 | */ |
| 192 | uint64_t counter:8; |
| 193 | } perfmon_command; |
| 194 | struct perfmon_status { |
| 195 | /* |
| 196 | * Resulting command status |
| 197 | */ |
| 198 | uint64_t val:8; |
| 199 | uint64_t unused:24; |
| 200 | } perfmon_status; |
| 201 | uint64_t data; |
| 202 | } uncore_perfmon_req_t; |
| 203 | |
| 204 | #define UNCORE_PERFMON_CMD_READ 0 |
| 205 | #define UNCORE_PERFMON_CMD_WRITE 1 |
| 206 | |
| 207 | #define UNCORE_PERFMON_CMD_MASK 0xFF |
| 208 | #define UNCORE_PERFMON_UNIT_GRP_MASK 0xF |
| 209 | #define UNCORE_PERFMON_SELECTOR_MASK 0xF |
| 210 | #define UNCORE_PERFMON_REG_MASK 0xFF |
| 211 | #define UNCORE_PERFMON_CTR_MASK 0xFF |
| 212 | #define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF |
| 213 | |
| 214 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 215 | * Structure populated by arch specific code to export routines which perform |
| 216 | * common low level MCE functions |
| 217 | ******************************************************************************/ |
| 218 | typedef struct arch_mce_ops { |
| 219 | /* |
| 220 | * This ARI request sets up the MCE to start execution on assertion |
| 221 | * of STANDBYWFI, update the core power state and expected wake time, |
| 222 | * then determine the proper power state to enter. |
| 223 | */ |
| 224 | int (*enter_cstate)(uint32_t ari_base, uint32_t state, |
| 225 | uint32_t wake_time); |
| 226 | /* |
| 227 | * This ARI request allows updating of the CLUSTER_CSTATE, |
| 228 | * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. |
| 229 | */ |
| 230 | int (*update_cstate_info)(uint32_t ari_base, |
| 231 | uint32_t cluster, |
| 232 | uint32_t ccplex, |
| 233 | uint32_t system, |
| 234 | uint8_t sys_state_force, |
| 235 | uint32_t wake_mask, |
| 236 | uint8_t update_wake_mask); |
| 237 | /* |
| 238 | * This ARI request allows updating of power state crossover |
| 239 | * threshold times. An index value specifies which crossover |
| 240 | * state is being updated. |
| 241 | */ |
| 242 | int (*update_crossover_time)(uint32_t ari_base, |
| 243 | uint32_t type, |
| 244 | uint32_t time); |
| 245 | /* |
| 246 | * This ARI request allows read access to statistical information |
| 247 | * related to power states. |
| 248 | */ |
| 249 | uint64_t (*read_cstate_stats)(uint32_t ari_base, |
| 250 | uint32_t state); |
| 251 | /* |
| 252 | * This ARI request allows write access to statistical information |
| 253 | * related to power states. |
| 254 | */ |
| 255 | int (*write_cstate_stats)(uint32_t ari_base, |
| 256 | uint32_t state, |
| 257 | uint32_t stats); |
| 258 | /* |
| 259 | * This ARI request allows the CPU to understand the features |
| 260 | * supported by the MCE firmware. |
| 261 | */ |
| 262 | uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, |
| 263 | uint32_t data); |
| 264 | /* |
| 265 | * This ARI request allows querying the CCPLEX to determine if |
| 266 | * the CCx state is allowed given a target core C-state and wake |
| 267 | * time. If the CCx state is allowed, the response indicates CCx |
| 268 | * must be entered. If the CCx state is not allowed, the response |
| 269 | * indicates CC6/CC7 can't be entered |
| 270 | */ |
| 271 | int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, |
| 272 | uint32_t wake_time); |
| 273 | /* |
| 274 | * This ARI request allows querying the CCPLEX to determine if |
| 275 | * the SC7 state is allowed given a target core C-state and wake |
| 276 | * time. If the SC7 state is allowed, all cores but the associated |
| 277 | * core are offlined (WAKE_EVENTS are set to 0) and the response |
| 278 | * indicates SC7 must be entered. If the SC7 state is not allowed, |
| 279 | * the response indicates SC7 can't be entered |
| 280 | */ |
| 281 | int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, |
| 282 | uint32_t wake_time); |
| 283 | /* |
| 284 | * This ARI request allows a core to bring another offlined core |
| 285 | * back online to the C0 state. Note that a core is offlined by |
| 286 | * entering a C-state where the WAKE_MASK is all 0. |
| 287 | */ |
| 288 | int (*online_core)(uint32_t ari_base, uint32_t cpuid); |
| 289 | /* |
| 290 | * This ARI request allows the CPU to enable/disable Auto-CC3 idle |
| 291 | * state. |
| 292 | */ |
| 293 | int (*cc3_ctrl)(uint32_t ari_base, |
| 294 | uint32_t freq, |
| 295 | uint32_t volt, |
| 296 | uint8_t enable); |
| 297 | /* |
| 298 | * This ARI request allows updating the reset vector register for |
| 299 | * D15 and A57 CPUs. |
| 300 | */ |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 301 | int (*update_reset_vector)(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 302 | /* |
| 303 | * This ARI request instructs the ROC to flush A57 data caches in |
| 304 | * order to maintain coherency with the Denver cluster. |
| 305 | */ |
| 306 | int (*roc_flush_cache)(uint32_t ari_base); |
| 307 | /* |
| 308 | * This ARI request instructs the ROC to flush A57 data caches along |
| 309 | * with the caches covering ARM code in order to maintain coherency |
| 310 | * with the Denver cluster. |
| 311 | */ |
| 312 | int (*roc_flush_cache_trbits)(uint32_t ari_base); |
| 313 | /* |
| 314 | * This ARI request instructs the ROC to clean A57 data caches along |
| 315 | * with the caches covering ARM code in order to maintain coherency |
| 316 | * with the Denver cluster. |
| 317 | */ |
| 318 | int (*roc_clean_cache)(uint32_t ari_base); |
| 319 | /* |
| 320 | * This ARI request reads/writes the Machine Check Arch. (MCA) |
| 321 | * registers. |
| 322 | */ |
| 323 | uint64_t (*read_write_mca)(uint32_t ari_base, |
| 324 | mca_cmd_t cmd, |
| 325 | uint64_t *data); |
| 326 | /* |
| 327 | * Some MC GSC (General Security Carveout) register values are |
| 328 | * expected to be changed by TrustZone secure ARM code after boot. |
| 329 | * Since there is no hardware mechanism for the CCPLEX to know |
| 330 | * that an MC GSC register has changed to allow it to update its |
| 331 | * own internal GSC register, there needs to be a mechanism that |
| 332 | * can be used by ARM code to cause the CCPLEX to update its GSC |
| 333 | * register value. This ARI request allows updating the GSC register |
| 334 | * value for a certain carveout in the CCPLEX. |
| 335 | */ |
| 336 | int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); |
| 337 | /* |
| 338 | * This ARI request instructs the CCPLEX to either shutdown or |
| 339 | * reset the entire system |
| 340 | */ |
| 341 | void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 342 | /* |
| 343 | * This ARI request reads/writes data from/to Uncore PERFMON |
| 344 | * registers |
| 345 | */ |
| 346 | int (*read_write_uncore_perfmon)(uint32_t ari_base, |
| 347 | uncore_perfmon_req_t req, uint64_t *data); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 348 | /* |
| 349 | * This ARI implements ARI_MISC_CCPLEX commands. This can be |
| 350 | * used to enable/disable coresight clock gating. |
| 351 | */ |
| 352 | void (*misc_ccplex)(uint32_t ari_base, uint32_t index, |
| 353 | uint32_t value); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 354 | } arch_mce_ops_t; |
| 355 | |
| 356 | int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, |
| 357 | uint64_t arg2); |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 358 | int mce_update_reset_vector(void); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 359 | int mce_update_gsc_videomem(void); |
| 360 | int mce_update_gsc_tzdram(void); |
| 361 | int mce_update_gsc_tzram(void); |
| 362 | __dead2 void mce_enter_ccplex_state(uint32_t state_idx); |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 363 | void mce_update_cstate_info(mce_cstate_info_t *cstate); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 364 | void mce_verify_firmware_version(void); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 365 | |
| 366 | /* declarations for ARI/NVG handler functions */ |
| 367 | int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 368 | int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
| 369 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 370 | uint8_t update_wake_mask); |
| 371 | int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); |
| 372 | uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); |
| 373 | int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); |
| 374 | uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); |
| 375 | int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 376 | int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 377 | int ari_online_core(uint32_t ari_base, uint32_t core); |
| 378 | int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 379 | int ari_reset_vector_update(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 380 | int ari_roc_flush_cache_trbits(uint32_t ari_base); |
| 381 | int ari_roc_flush_cache(uint32_t ari_base); |
| 382 | int ari_roc_clean_cache(uint32_t ari_base); |
| 383 | uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data); |
| 384 | int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); |
| 385 | void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 386 | int ari_read_write_uncore_perfmon(uint32_t ari_base, |
| 387 | uncore_perfmon_req_t req, uint64_t *data); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 388 | void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 389 | |
| 390 | int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 391 | int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
| 392 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 393 | uint8_t update_wake_mask); |
| 394 | int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); |
| 395 | uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); |
| 396 | int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); |
| 397 | int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 398 | int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 399 | int nvg_online_core(uint32_t ari_base, uint32_t core); |
| 400 | int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); |
| 401 | |
| 402 | #endif /* __MCE_H__ */ |