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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001ARM Trusted Firmware User Guide
2===============================
3
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
10This document describes how to build ARM Trusted Firmware (TF) and run it with a
11tested set of other software components using defined configurations on the Juno
12ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is
13possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
41The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for
42building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
51Install the required packages to build Trusted Firmware with the following
52command:
53
54::
55
56 sudo apt-get install build-essential gcc make git libssl-dev
57
David Cunado82509be2017-12-19 16:33:25 +000058ARM TF has been tested with `Linaro Release 17.10`_.
David Cunadob2de0992017-06-29 12:01:33 +010059
Douglas Raillardd7c21b72017-06-28 15:23:03 +010060Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010061The `Linaro Release Notes`_ documents which version of the compiler to use for a
62given Linaro Release. Also, these `Linaro instructions`_ provide further
63guidance and a script, which can be used to download Linaro deliverables
64automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065
66Optionally, Trusted Firmware can be built using clang or ARM Compiler 6.
67See instructions below on how to switch the default compiler.
68
69In addition, the following optional packages and tools may be needed:
70
71- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
72 Tree (FDT) source files (``.dts`` files) provided with this software.
73
74- For debugging, ARM `Development Studio 5 (DS-5)`_.
75
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
78 generate the actual *.png files.
79
Douglas Raillardd7c21b72017-06-28 15:23:03 +010080Getting the Trusted Firmware source code
81----------------------------------------
82
83Download the Trusted Firmware source code from Github:
84
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
89Building the Trusted Firmware
90-----------------------------
91
92- Before building Trusted Firmware, the environment variable ``CROSS_COMPILE``
93 must point to the Linaro cross compiler.
94
95 For AArch64:
96
97 ::
98
99 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
100
101 For AArch32:
102
103 ::
104
105 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
106
107 It is possible to build Trusted Firmware using clang or ARM Compiler 6.
108 To do so ``CC`` needs to point to the clang or armclang binary. Only the
109 compiler is switched; the assembler and linker need to be provided by
110 the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above.
111
112 ARM Compiler 6 will be selected when the base name of the path assigned
113 to ``CC`` matches the string 'armclang'.
114
115 For AArch64 using ARM Compiler 6:
116
117 ::
118
119 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
120 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
121
122 Clang will be selected when the base name of the path assigned to ``CC``
123 contains the string 'clang'. This is to allow both clang and clang-X.Y
124 to work.
125
126 For AArch64 using clang:
127
128 ::
129
130 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
131 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
132
133- Change to the root directory of the Trusted Firmware source tree and build.
134
135 For AArch64:
136
137 ::
138
139 make PLAT=<platform> all
140
141 For AArch32:
142
143 ::
144
145 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
146
147 Notes:
148
149 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
150 `Summary of build options`_ for more information on available build
151 options.
152
153 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
154
155 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
156 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
157 provided by ARM Trusted Firmware to demonstrate how PSCI Library can
158 be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3
159 Runtime Software may include other runtime services, for example
160 Trusted OS services. A guide to integrate PSCI library with AArch32
161 EL3 Runtime Software can be found `here`_.
162
163 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
164 image, is not compiled in by default. Refer to the
165 `Building the Test Secure Payload`_ section below.
166
167 - By default this produces a release version of the build. To produce a
168 debug version instead, refer to the "Debugging options" section below.
169
170 - The build process creates products in a ``build`` directory tree, building
171 the objects and binaries for each boot loader stage in separate
172 sub-directories. The following boot loader binary files are created
173 from the corresponding ELF files:
174
175 - ``build/<platform>/<build-type>/bl1.bin``
176 - ``build/<platform>/<build-type>/bl2.bin``
177 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
178 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
179
180 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
181 is either ``debug`` or ``release``. The actual number of images might differ
182 depending on the platform.
183
184- Build products for a specific build variant can be removed using:
185
186 ::
187
188 make DEBUG=<D> PLAT=<platform> clean
189
190 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
191
192 The build tree can be removed completely using:
193
194 ::
195
196 make realclean
197
198Summary of build options
199~~~~~~~~~~~~~~~~~~~~~~~~
200
201ARM Trusted Firmware build system supports the following build options. Unless
202mentioned otherwise, these options are expected to be specified at the build
203command line and are not to be modified in any component makefiles. Note that
204the build system doesn't track dependency for build options. Therefore, if any
205of the build options are changed from a previous build, a clean build must be
206performed.
207
208Common build options
209^^^^^^^^^^^^^^^^^^^^
210
211- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
212 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
213 directory containing the SP source, relative to the ``bl32/``; the directory
214 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
215
216- ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware.
217 It can take either ``aarch64`` or ``aarch32`` as values. By default, it is
218 defined to ``aarch64``.
219
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100220- ``ARM_ARCH_MAJOR``: The major version of ARM Architecture to target when
221 compiling ARM Trusted Firmware. Its value must be numeric, and defaults to
Etienne Carriere1374fcb2017-11-08 13:48:40 +0100222 8 . See also, *ARMv8 Architecture Extensions* and
223 *ARMv7 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100224
225- ``ARM_ARCH_MINOR``: The minor version of ARM Architecture to target when
226 compiling ARM Trusted Firmware. Its value must be a numeric, and defaults
227 to 0. See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
228
229- ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM
230 Legacy GIC driver for implementing the platform GIC API. This API is used
231 by the interrupt management framework. Default is 2 (that is, version 2.0).
232 This build option is deprecated.
233
234- ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000235 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
236 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
237 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
238 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100239
240- ``BL2``: This is an optional build option which specifies the path to BL2
241 image for the ``fip`` target. In this case, the BL2 in the ARM Trusted
242 Firmware will not be built.
243
244- ``BL2U``: This is an optional build option which specifies the path to
245 BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not
246 be built.
247
248- ``BL31``: This is an optional build option which specifies the path to
249 BL31 image for the ``fip`` target. In this case, the BL31 in the ARM
250 Trusted Firmware will not be built.
251
252- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
253 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
254 this file name will be used to save the key.
255
256- ``BL32``: This is an optional build option which specifies the path to
257 BL32 image for the ``fip`` target. In this case, the BL32 in the ARM
258 Trusted Firmware will not be built.
259
Summer Qin80726782017-04-20 16:28:39 +0100260- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
261 Trusted OS Extra1 image for the ``fip`` target.
262
263- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
264 Trusted OS Extra2 image for the ``fip`` target.
265
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
267 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
268 this file name will be used to save the key.
269
270- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
271 ``fip`` target in case the BL2 from ARM Trusted Firmware is used.
272
273- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
274 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
275 this file name will be used to save the key.
276
277- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
278 compilation of each build. It must be set to a C string (including quotes
279 where applicable). Defaults to a string that contains the time and date of
280 the compilation.
281
282- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build
283 to be uniquely identified. Defaults to the current git commit id.
284
285- ``CFLAGS``: Extra user options appended on the compiler's command line in
286 addition to the options set by the build system.
287
288- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
289 release several CPUs out of reset. It can take either 0 (several CPUs may be
290 brought up) or 1 (only one CPU will ever be brought up during cold reset).
291 Default is 0. If the platform always brings up a single CPU, there is no
292 need to distinguish between primary and secondary CPUs and the boot path can
293 be optimised. The ``plat_is_my_cpu_primary()`` and
294 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
295 to be implemented in this case.
296
297- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
298 register state when an unexpected exception occurs during execution of
299 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
300 this is only enabled for a debug build of the firmware.
301
302- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
303 certificate generation tool to create new keys in case no valid keys are
304 present or specified. Allowed options are '0' or '1'. Default is '1'.
305
306- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
307 the AArch32 system registers to be included when saving and restoring the
308 CPU context. The option must be set to 0 for AArch64-only platforms (that
309 is on hardware that does not implement AArch32, or at least not at EL1 and
310 higher ELs). Default value is 1.
311
312- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
313 registers to be included when saving and restoring the CPU context. Default
314 is 0.
315
316- ``DEBUG``: Chooses between a debug and release build. It can take either 0
317 (release) or 1 (debug) as values. 0 is the default.
318
319- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
320 the normal boot flow. It must specify the entry point address of the EL3
321 payload. Please refer to the "Booting an EL3 payload" section for more
322 details.
323
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100324- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100325 This is an optional architectural feature available on v8.4 onwards. Some
326 v8.2 implementations also implement an AMU and this option can be used to
327 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100328
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100329- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
330 are compiled out. For debug builds, this option defaults to 1, and calls to
331 ``assert()`` are left in place. For release builds, this option defaults to 0
332 and calls to ``assert()`` function are compiled out. This option can be set
333 independently of ``DEBUG``. It can also be used to hide any auxiliary code
334 that is only required for the assertion and does not fit in the assertion
335 itself.
336
337- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
338 Measurement Framework(PMF). Default is 0.
339
340- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
341 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
342 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
343 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
344 software.
345
346- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
347 instrumentation which injects timestamp collection points into
348 Trusted Firmware to allow runtime performance to be measured.
349 Currently, only PSCI is instrumented. Enabling this option enables
350 the ``ENABLE_PMF`` build option as well. Default is 0.
351
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100352- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100353 extensions. This is an optional architectural feature for AArch64.
354 The default is 1 but is automatically disabled when the target architecture
355 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100356
David Cunadoce88eee2017-10-20 11:30:57 +0100357- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
358 (SVE) for the Non-secure world only. SVE is an optional architectural feature
359 for AArch64. Note that when SVE is enabled for the Non-secure world, access
360 to SIMD and floating-point functionality from the Secure world is disabled.
361 This is to avoid corruption of the Non-secure world data in the Z-registers
362 which are aliased by the SIMD and FP registers. The build option is not
363 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
364 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
365 1. The default is 1 but is automatically disabled when the target
366 architecture is AArch32.
367
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100368- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
369 checks in GCC. Allowed values are "all", "strong" and "0" (default).
370 "strong" is the recommended stack protection level if this feature is
371 desired. 0 disables the stack protection. For all values other than 0, the
372 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
373 The value is passed as the last component of the option
374 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
375
376- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
377 deprecated platform APIs, helper functions or drivers within Trusted
378 Firmware as error. It can take the value 1 (flag the use of deprecated
379 APIs as error) or 0. The default is 0.
380
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100381- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
382 targeted at EL3. When set ``0`` (default), no exceptions are expected or
383 handled at EL3, and a panic will result. This is supported only for AArch64
384 builds.
385
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100386- ``FIP_NAME``: This is an optional build option which specifies the FIP
387 filename for the ``fip`` target. Default is ``fip.bin``.
388
389- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
390 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
391
392- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
393 tool to create certificates as per the Chain of Trust described in
394 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
395 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
396
397 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
398 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
399 the corresponding certificates, and to include those certificates in the
400 FIP and FWU\_FIP.
401
402 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
403 images will not include support for Trusted Board Boot. The FIP will still
404 include the corresponding certificates. This FIP can be used to verify the
405 Chain of Trust on the host machine through other mechanisms.
406
407 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
408 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
409 will not include the corresponding certificates, causing a boot failure.
410
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100411- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
412 inherent support for specific EL3 type interrupts. Setting this build option
413 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
414 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
415 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
416 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
417 the Secure Payload interrupts needs to be synchronously handed over to Secure
418 EL1 for handling. The default value of this option is ``0``, which means the
419 Group 0 interrupts are assumed to be handled by Secure EL1.
420
421 .. __: `platform-interrupt-controller-API.rst`
422 .. __: `interrupt-framework-design.rst`
423
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100424- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
425 will be always trapped in EL3 i.e. in BL31 at runtime.
426
427- ``HW_ASSISTED_COHERENCY``: On most ARM systems to-date, platform-specific
428 software operations are required for CPUs to enter and exit coherency.
429 However, there exists newer systems where CPUs' entry to and exit from
430 coherency is managed in hardware. Such systems require software to only
431 initiate the operations, and the rest is managed in hardware, minimizing
432 active software management. In such systems, this boolean option enables ARM
433 Trusted Firmware to carry out build and run-time optimizations during boot
434 and power management operations. This option defaults to 0 and if it is
435 enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
436
437- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
438 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
439 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
440 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
441 images.
442
Soby Mathew13b16052017-08-31 11:49:32 +0100443- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
444 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800445 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100446 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
447 retained only for compatibility. The default value of this flag is ``rsa``
448 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100449
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800450- ``HASH_ALG``: This build flag enables the user to select the secure hash
451 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
452 The default value of this flag is ``sha256``.
453
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100454- ``LDFLAGS``: Extra user options appended to the linkers' command line in
455 addition to the one set by the build system.
456
457- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
458 image loading, which provides more flexibility and scalability around what
459 images are loaded and executed during boot. Default is 0.
460 Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
461 ``LOAD_IMAGE_V2`` is enabled.
462
463- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
464 output compiled into the build. This should be one of the following:
465
466 ::
467
468 0 (LOG_LEVEL_NONE)
469 10 (LOG_LEVEL_NOTICE)
470 20 (LOG_LEVEL_ERROR)
471 30 (LOG_LEVEL_WARNING)
472 40 (LOG_LEVEL_INFO)
473 50 (LOG_LEVEL_VERBOSE)
474
475 All log output up to and including the log level is compiled into the build.
476 The default value is 40 in debug builds and 20 in release builds.
477
478- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
479 specifies the file that contains the Non-Trusted World private key in PEM
480 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
481
482- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
483 optional. It is only needed if the platform makefile specifies that it
484 is required in order to build the ``fwu_fip`` target.
485
486- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
487 contents upon world switch. It can take either 0 (don't save and restore) or
488 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
489 wants the timer registers to be saved and restored.
490
491- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
492 the underlying hardware is not a full PL011 UART but a minimally compliant
493 generic UART, which is a subset of the PL011. The driver will not access
494 any register that is not part of the SBSA generic UART specification.
495 Default value is 0 (a full PL011 compliant UART is present).
496
497- ``PLAT``: Choose a platform to build ARM Trusted Firmware for. The chosen
498 platform name must be subdirectory of any depth under ``plat/``, and must
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +0100499 contain a platform makefile named ``platform.mk``. For example to build ARM
500 Trusted Firmware for ARM Juno board select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100501
502- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
503 instead of the normal boot flow. When defined, it must specify the entry
504 point address for the preloaded BL33 image. This option is incompatible with
505 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
506 over ``PRELOADED_BL33_BASE``.
507
508- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
509 vector address can be programmed or is fixed on the platform. It can take
510 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
511 programmable reset address, it is expected that a CPU will start executing
512 code directly at the right address, both on a cold and warm reset. In this
513 case, there is no need to identify the entrypoint on boot and the boot path
514 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
515 does not need to be implemented in this case.
516
517- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
518 possible for the PSCI power-state parameter viz original and extended
519 State-ID formats. This flag if set to 1, configures the generic PSCI layer
520 to use the extended format. The default value of this flag is 0, which
521 means by default the original power-state format is used by the PSCI
522 implementation. This flag should be specified by the platform makefile
523 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
524 smc function id. When this option is enabled on ARM platforms, the
525 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
526
527- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
528 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
529 entrypoint) or 1 (CPU reset to BL31 entrypoint).
530 The default value is 0.
531
532- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in
533 ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU
534 reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
535 reset to BL1 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default
536 value is 0.
537
538- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
539 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
540 file name will be used to save the key.
541
542- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
543 certificate generation tool to save the keys used to establish the Chain of
544 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
545
546- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
547 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
548 target.
549
550- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
551 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
552 this file name will be used to save the key.
553
554- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
555 optional. It is only needed if the platform makefile specifies that it
556 is required in order to build the ``fwu_fip`` target.
557
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100558- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
559 Delegated Exception Interface to BL31 image. This defaults to ``0``.
560
561 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
562 set to ``1``.
563
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100564- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
565 isolated on separate memory pages. This is a trade-off between security and
566 memory usage. See "Isolating code and read-only data on separate memory
567 pages" section in `Firmware Design`_. This flag is disabled by default and
568 affects all BL images.
569
570- ``SPD``: Choose a Secure Payload Dispatcher component to be built into the
571 Trusted Firmware. This build option is only valid if ``ARCH=aarch64``. The
572 value should be the path to the directory containing the SPD source,
573 relative to ``services/spd/``; the directory is expected to
574 contain a makefile called ``<spd-value>.mk``.
575
576- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
577 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
578 execution in BL1 just before handing over to BL31. At this point, all
579 firmware images have been loaded in memory, and the MMU and caches are
580 turned off. Refer to the "Debugging options" section for more details.
581
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200582- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
583 secure interrupts (caught through the FIQ line). Platforms can enable
584 this directive if they need to handle such interruption. When enabled,
585 the FIQ are handled in monitor mode and non secure world is not allowed
586 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
587 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
588
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100589- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
590 Boot feature. When set to '1', BL1 and BL2 images include support to load
591 and verify the certificates and images in a FIP, and BL1 includes support
592 for the Firmware Update. The default value is '0'. Generation and inclusion
593 of certificates in the FIP and FWU\_FIP depends upon the value of the
594 ``GENERATE_COT`` option.
595
596 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
597 already exist in disk, they will be overwritten without further notice.
598
599- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
600 specifies the file that contains the Trusted World private key in PEM
601 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
602
603- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
604 synchronous, (see "Initializing a BL32 Image" section in
605 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
606 synchronous method) or 1 (BL32 is initialized using asynchronous method).
607 Default is 0.
608
609- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
610 routing model which routes non-secure interrupts asynchronously from TSP
611 to EL3 causing immediate preemption of TSP. The EL3 is responsible
612 for saving and restoring the TSP context in this routing model. The
613 default routing model (when the value is 0) is to route non-secure
614 interrupts to TSP allowing it to save its context and hand over
615 synchronously to EL3 via an SMC.
616
617- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
618 memory region in the BL memory map or not (see "Use of Coherent memory in
619 Trusted Firmware" section in `Firmware Design`_). It can take the value 1
620 (Coherent memory region is included) or 0 (Coherent memory region is
621 excluded). Default is 1.
622
623- ``V``: Verbose build. If assigned anything other than 0, the build commands
624 are printed. Default is 0.
625
626- ``VERSION_STRING``: String used in the log output for each TF image. Defaults
627 to a string formed by concatenating the version number, build type and build
628 string.
629
630- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
631 the CPU after warm boot. This is applicable for platforms which do not
632 require interconnect programming to enable cache coherency (eg: single
633 cluster platforms). If this option is enabled, then warm boot path
634 enables D-caches immediately after enabling MMU. This option defaults to 0.
635
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100636ARM development platform specific build options
637^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
638
639- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
640 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
641 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
642 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
643 flag.
644
645- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
646 of the memory reserved for each image. This affects the maximum size of each
647 BL image as well as the number of allocated memory regions and translation
648 tables. By default this flag is 0, which means it uses the default
649 unoptimised values for these macros. ARM development platforms that wish to
650 optimise memory usage need to set this flag to 1 and must override the
651 related macros.
652
653- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
654 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
655 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
656 match the frame used by the Non-Secure image (normally the Linux kernel).
657 Default is true (access to the frame is allowed).
658
659- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
660 By default, ARM platforms use a watchdog to trigger a system reset in case
661 an error is encountered during the boot process (for example, when an image
662 could not be loaded or authenticated). The watchdog is enabled in the early
663 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
664 Trusted Watchdog may be disabled at build time for testing or development
665 purposes.
666
667- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
668 for the construction of composite state-ID in the power-state parameter.
669 The existing PSCI clients currently do not support this encoding of
670 State-ID yet. Hence this flag is used to configure whether to use the
671 recommended State-ID encoding or not. The default value of this flag is 0,
672 in which case the platform is configured to expect NULL in the State-ID
673 field of power-state parameter.
674
675- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
676 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
677 for ARM platforms. Depending on the selected option, the proper private key
678 must be specified using the ``ROT_KEY`` option when building the Trusted
679 Firmware. This private key will be used by the certificate generation tool
680 to sign the BL2 and Trusted Key certificates. Available options for
681 ``ARM_ROTPK_LOCATION`` are:
682
683 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
684 registers. The private key corresponding to this ROTPK hash is not
685 currently available.
686 - ``devel_rsa`` : return a development public key hash embedded in the BL1
687 and BL2 binaries. This hash has been obtained from the RSA public key
688 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
689 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
690 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800691 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
692 and BL2 binaries. This hash has been obtained from the ECDSA public key
693 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
694 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
695 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100696
697- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
698
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800699 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100700 - ``tdram`` : Trusted DRAM (if available)
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800701 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
702 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100703
704- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware
705 with version 1 of the translation tables library instead of version 2. It is
706 set to 0 by default, which selects version 2.
707
708- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable Trusted Firmware to invoke
709 ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
710 ARM platforms. If this option is specified, then the path to the CryptoCell
711 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
712
713For a better understanding of these options, the ARM development platform memory
714map is explained in the `Firmware Design`_.
715
716ARM CSS platform specific build options
717^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
718
719- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
720 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
721 compatible change to the MTL protocol, used for AP/SCP communication.
722 Trusted Firmware no longer supports earlier SCP versions. If this option is
723 set to 1 then Trusted Firmware will detect if an earlier version is in use.
724 Default is 1.
725
726- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
727 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
728 during boot. Default is 1.
729
Soby Mathew1ced6b82017-06-12 12:37:10 +0100730- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
731 instead of SCPI/BOM driver for communicating with the SCP during power
732 management operations and for SCP RAM Firmware transfer. If this option
733 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100734
735ARM FVP platform specific build options
736^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
737
738- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
739 build the topology tree within Trusted Firmware. By default the
740 Trusted Firmware is configured for dual cluster topology and this option
741 can be used to override the default value.
742
743- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
744 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
745 explained in the options below:
746
747 - ``FVP_CCI`` : The CCI driver is selected. This is the default
748 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
749 - ``FVP_CCN`` : The CCN driver is selected. This is the default
750 if ``FVP_CLUSTER_COUNT`` > 2.
751
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000752- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
753 in the system. This option defaults to 1. Note that the build option
754 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
755
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100756- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
757
758 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
759 - ``FVP_GICV2`` : The GICv2 only driver is selected
760 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
761 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
762 Note: If Trusted Firmware is compiled with this option on FVPs with
763 GICv3 hardware, then it configures the hardware to run in GICv2
764 emulation mode
765
766- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
767 for functions that wait for an arbitrary time length (udelay and mdelay).
768 The default value is 0.
769
770Debugging options
771~~~~~~~~~~~~~~~~~
772
773To compile a debug version and make the build more verbose use
774
775::
776
777 make PLAT=<platform> DEBUG=1 V=1 all
778
779AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
780example DS-5) might not support this and may need an older version of DWARF
781symbols to be emitted by GCC. This can be achieved by using the
782``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
783version to 2 is recommended for DS-5 versions older than 5.16.
784
785When debugging logic problems it might also be useful to disable all compiler
786optimizations by using ``-O0``.
787
788NOTE: Using ``-O0`` could cause output images to be larger and base addresses
789might need to be recalculated (see the **Memory layout on ARM development
790platforms** section in the `Firmware Design`_).
791
792Extra debug options can be passed to the build system by setting ``CFLAGS`` or
793``LDFLAGS``:
794
795.. code:: makefile
796
797 CFLAGS='-O0 -gdwarf-2' \
798 make PLAT=<platform> DEBUG=1 V=1 all
799
800Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
801ignored as the linker is called directly.
802
803It is also possible to introduce an infinite loop to help in debugging the
804post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
Douglas Raillard30d7b362017-06-28 16:14:55 +0100805the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100806section. In this case, the developer may take control of the target using a
807debugger when indicated by the console output. When using DS-5, the following
808commands can be used:
809
810::
811
812 # Stop target execution
813 interrupt
814
815 #
816 # Prepare your debugging environment, e.g. set breakpoints
817 #
818
819 # Jump over the debug loop
820 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
821
822 # Resume execution
823 continue
824
825Building the Test Secure Payload
826~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
827
828The TSP is coupled with a companion runtime service in the BL31 firmware,
829called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
830must be recompiled as well. For more information on SPs and SPDs, see the
831`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
832
833First clean the Trusted Firmware build directory to get rid of any previous
834BL31 binary. Then to build the TSP image use:
835
836::
837
838 make PLAT=<platform> SPD=tspd all
839
840An additional boot loader binary file is created in the ``build`` directory:
841
842::
843
844 build/<platform>/<build-type>/bl32.bin
845
846Checking source code style
847~~~~~~~~~~~~~~~~~~~~~~~~~~
848
849When making changes to the source for submission to the project, the source
850must be in compliance with the Linux style guide, and to assist with this check
851the project Makefile contains two targets, which both utilise the
852``checkpatch.pl`` script that ships with the Linux source tree.
853
854To check the entire source tree, you must first download a copy of
855``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
856variable to point to the script and build the target checkcodebase:
857
858::
859
860 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
861
862To just check the style on the files that differ between your local branch and
863the remote master, use:
864
865::
866
867 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
868
869If you wish to check your patch against something other than the remote master,
870set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
871is set to ``origin/master``.
872
873Building and using the FIP tool
874~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
875
876Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
877project to package firmware images in a single binary. The number and type of
878images that should be packed in a FIP is platform specific and may include TF
879images and other firmware images required by the platform. For example, most
880platforms require a BL33 image which corresponds to the normal world bootloader
881(e.g. UEFI or U-Boot).
882
883The TF build system provides the make target ``fip`` to create a FIP file for the
884specified platform using the FIP creation tool included in the TF project.
885Examples below show how to build a FIP file for FVP, packaging TF images and a
886BL33 image.
887
888For AArch64:
889
890::
891
892 make PLAT=fvp BL33=<path/to/bl33.bin> fip
893
894For AArch32:
895
896::
897
898 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
899
900Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
901UEFI, on FVP is not available upstream. Hence custom solutions are required to
902allow Linux boot on FVP. These instructions assume such a custom boot loader
903(BL33) is available.
904
905The resulting FIP may be found in:
906
907::
908
909 build/fvp/<build-type>/fip.bin
910
911For advanced operations on FIP files, it is also possible to independently build
912the tool and create or modify FIPs using this tool. To do this, follow these
913steps:
914
915It is recommended to remove old artifacts before building the tool:
916
917::
918
919 make -C tools/fiptool clean
920
921Build the tool:
922
923::
924
925 make [DEBUG=1] [V=1] fiptool
926
927The tool binary can be located in:
928
929::
930
931 ./tools/fiptool/fiptool
932
933Invoking the tool with ``--help`` will print a help message with all available
934options.
935
936Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
937
938::
939
940 ./tools/fiptool/fiptool create \
941 --tb-fw build/<platform>/<build-type>/bl2.bin \
942 --soc-fw build/<platform>/<build-type>/bl31.bin \
943 fip.bin
944
945Example 2: view the contents of an existing Firmware package:
946
947::
948
949 ./tools/fiptool/fiptool info <path-to>/fip.bin
950
951Example 3: update the entries of an existing Firmware package:
952
953::
954
955 # Change the BL2 from Debug to Release version
956 ./tools/fiptool/fiptool update \
957 --tb-fw build/<platform>/release/bl2.bin \
958 build/<platform>/debug/fip.bin
959
960Example 4: unpack all entries from an existing Firmware package:
961
962::
963
964 # Images will be unpacked to the working directory
965 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
966
967Example 5: remove an entry from an existing Firmware package:
968
969::
970
971 ./tools/fiptool/fiptool remove \
972 --tb-fw build/<platform>/debug/fip.bin
973
974Note that if the destination FIP file exists, the create, update and
975remove operations will automatically overwrite it.
976
977The unpack operation will fail if the images already exist at the
978destination. In that case, use -f or --force to continue.
979
980More information about FIP can be found in the `Firmware Design`_ document.
981
982Migrating from fip\_create to fiptool
983^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
984
985The previous version of fiptool was called fip\_create. A compatibility script
986that emulates the basic functionality of the previous fip\_create is provided.
987However, users are strongly encouraged to migrate to fiptool.
988
989- To create a new FIP file, replace "fip\_create" with "fiptool create".
990- To update a FIP file, replace "fip\_create" with "fiptool update".
991- To dump the contents of a FIP file, replace "fip\_create --dump"
992 with "fiptool info".
993
994Building FIP images with support for Trusted Board Boot
995~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
996
997Trusted Board Boot primarily consists of the following two features:
998
999- Image Authentication, described in `Trusted Board Boot`_, and
1000- Firmware Update, described in `Firmware Update`_
1001
1002The following steps should be followed to build FIP and (optionally) FWU\_FIP
1003images with support for these features:
1004
1005#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1006 modules by checking out a recent version of the `mbed TLS Repository`_. It
1007 is important to use a version that is compatible with TF and fixes any
1008 known security vulnerabilities. See `mbed TLS Security Center`_ for more
David Cunado82509be2017-12-19 16:33:25 +00001009 information. The latest version of TF is tested with tag ``mbedtls-2.6.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001010
1011 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1012 source files the modules depend upon.
1013 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1014 options required to build the mbed TLS sources.
1015
1016 Note that the mbed TLS library is licensed under the Apache version 2.0
1017 license. Using mbed TLS source code will affect the licensing of
1018 Trusted Firmware binaries that are built using this library.
1019
1020#. To build the FIP image, ensure the following command line variables are set
1021 while invoking ``make`` to build Trusted Firmware:
1022
1023 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1024 - ``TRUSTED_BOARD_BOOT=1``
1025 - ``GENERATE_COT=1``
1026
1027 In the case of ARM platforms, the location of the ROTPK hash must also be
1028 specified at build time. Two locations are currently supported (see
1029 ``ARM_ROTPK_LOCATION`` build option):
1030
1031 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1032 root-key storage registers present in the platform. On Juno, this
1033 registers are read-only. On FVP Base and Cortex models, the registers
1034 are read-only, but the value can be specified using the command line
1035 option ``bp.trusted_key_storage.public_key`` when launching the model.
1036 On both Juno and FVP models, the default value corresponds to an
1037 ECDSA-SECP256R1 public key hash, whose private part is not currently
1038 available.
1039
1040 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1041 in the ARM platform port. The private/public RSA key pair may be
1042 found in ``plat/arm/board/common/rotpk``.
1043
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001044 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1045 in the ARM platform port. The private/public ECDSA key pair may be
1046 found in ``plat/arm/board/common/rotpk``.
1047
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001048 Example of command line using RSA development keys:
1049
1050 ::
1051
1052 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1053 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1054 ARM_ROTPK_LOCATION=devel_rsa \
1055 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1056 BL33=<path-to>/<bl33_image> \
1057 all fip
1058
1059 The result of this build will be the bl1.bin and the fip.bin binaries. This
1060 FIP will include the certificates corresponding to the Chain of Trust
1061 described in the TBBR-client document. These certificates can also be found
1062 in the output build directory.
1063
1064#. The optional FWU\_FIP contains any additional images to be loaded from
1065 Non-Volatile storage during the `Firmware Update`_ process. To build the
1066 FWU\_FIP, any FWU images required by the platform must be specified on the
1067 command line. On ARM development platforms like Juno, these are:
1068
1069 - NS\_BL2U. The AP non-secure Firmware Updater image.
1070 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1071
1072 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1073 targets using RSA development:
1074
1075 ::
1076
1077 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1078 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1079 ARM_ROTPK_LOCATION=devel_rsa \
1080 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1081 BL33=<path-to>/<bl33_image> \
1082 SCP_BL2=<path-to>/<scp_bl2_image> \
1083 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1084 NS_BL2U=<path-to>/<ns_bl2u_image> \
1085 all fip fwu_fip
1086
1087 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1088 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1089 to the command line above.
1090
1091 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1092 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1093
1094 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1095 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1096 Chain of Trust described in the TBBR-client document. These certificates
1097 can also be found in the output build directory.
1098
1099Building the Certificate Generation Tool
1100~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1101
1102The ``cert_create`` tool is built as part of the TF build process when the ``fip``
1103make target is specified and TBB is enabled (as described in the previous
1104section), but it can also be built separately with the following command:
1105
1106::
1107
1108 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1109
1110For platforms that do not require their own IDs in certificate files,
1111the generic 'cert\_create' tool can be built with the following command:
1112
1113::
1114
1115 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1116
1117``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1118verbose. The following command should be used to obtain help about the tool:
1119
1120::
1121
1122 ./tools/cert_create/cert_create -h
1123
1124Building a FIP for Juno and FVP
1125-------------------------------
1126
1127This section provides Juno and FVP specific instructions to build Trusted
1128Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001129a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001130
David Cunadob2de0992017-06-29 12:01:33 +01001131Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1132onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001133
1134Note: follow the full instructions for one platform before switching to a
1135different one. Mixing instructions for different platforms may result in
1136corrupted binaries.
1137
1138#. Clean the working directory
1139
1140 ::
1141
1142 make realclean
1143
1144#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1145
1146 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1147 package included in the Linaro release:
1148
1149 ::
1150
1151 # Build the fiptool
1152 make [DEBUG=1] [V=1] fiptool
1153
1154 # Unpack firmware images from Linaro FIP
1155 ./tools/fiptool/fiptool unpack \
1156 <path/to/linaro/release>/fip.bin
1157
1158 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001159 current working directory. The SCP\_BL2 image corresponds to
1160 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001161
1162 Note: the fiptool will complain if the images to be unpacked already
1163 exist in the current directory. If that is the case, either delete those
1164 files or use the ``--force`` option to overwrite.
1165
1166 Note for AArch32, the instructions below assume that nt-fw.bin is a custom
1167 Normal world boot loader that supports AArch32.
1168
1169#. Build TF images and create a new FIP for FVP
1170
1171 ::
1172
1173 # AArch64
1174 make PLAT=fvp BL33=nt-fw.bin all fip
1175
1176 # AArch32
1177 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1178
1179#. Build TF images and create a new FIP for Juno
1180
1181 For AArch64:
1182
1183 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1184 as a build parameter.
1185
1186 ::
1187
1188 make PLAT=juno all fip \
1189 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1190 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1191
1192 For AArch32:
1193
1194 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1195 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1196 separately for AArch32.
1197
1198 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1199 to the AArch32 Linaro cross compiler.
1200
1201 ::
1202
1203 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1204
1205 - Build BL32 in AArch32.
1206
1207 ::
1208
1209 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1210 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1211
1212 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1213 must point to the AArch64 Linaro cross compiler.
1214
1215 ::
1216
1217 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1218
1219 - The following parameters should be used to build BL1 and BL2 in AArch64
1220 and point to the BL32 file.
1221
1222 ::
1223
1224 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1225 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001226 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001227 BL32=<path-to-bl32>/bl32.bin all fip
1228
1229The resulting BL1 and FIP images may be found in:
1230
1231::
1232
1233 # Juno
1234 ./build/juno/release/bl1.bin
1235 ./build/juno/release/fip.bin
1236
1237 # FVP
1238 ./build/fvp/release/bl1.bin
1239 ./build/fvp/release/fip.bin
1240
Roberto Vargas096f3a02017-10-17 10:19:00 +01001241
1242Booting Firmware Update images
1243-------------------------------------
1244
1245When Firmware Update (FWU) is enabled there are at least 2 new images
1246that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1247FWU FIP.
1248
1249Juno
1250~~~~
1251
1252The new images must be programmed in flash memory by adding
1253an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1254on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1255Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1256programming" for more information. User should ensure these do not
1257overlap with any other entries in the file.
1258
1259::
1260
1261 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1262 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1263 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1264 NOR10LOAD: 00000000 ;Image Load Address
1265 NOR10ENTRY: 00000000 ;Image Entry Point
1266
1267 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1268 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1269 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1270 NOR11LOAD: 00000000 ;Image Load Address
1271
1272The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1273In the same way, the address ns_bl2u_base_address is the value of
1274NS_BL2U_BASE - 0x8000000.
1275
1276FVP
1277~~~
1278
1279The additional fip images must be loaded with:
1280
1281::
1282
1283 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1284 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1285
1286The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1287In the same way, the address ns_bl2u_base_address is the value of
1288NS_BL2U_BASE.
1289
1290
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001291EL3 payloads alternative boot flow
1292----------------------------------
1293
1294On a pre-production system, the ability to execute arbitrary, bare-metal code at
1295the highest exception level is required. It allows full, direct access to the
1296hardware, for example to run silicon soak tests.
1297
1298Although it is possible to implement some baremetal secure firmware from
1299scratch, this is a complex task on some platforms, depending on the level of
1300configuration required to put the system in the expected state.
1301
1302Rather than booting a baremetal application, a possible compromise is to boot
1303``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an
1304alternative boot flow, where a modified BL2 boots an EL3 payload, instead of
1305loading the other BL images and passing control to BL31. It reduces the
1306complexity of developing EL3 baremetal code by:
1307
1308- putting the system into a known architectural state;
1309- taking care of platform secure world initialization;
1310- loading the SCP\_BL2 image if required by the platform.
1311
1312When booting an EL3 payload on ARM standard platforms, the configuration of the
1313TrustZone controller is simplified such that only region 0 is enabled and is
1314configured to permit secure access only. This gives full access to the whole
1315DRAM to the EL3 payload.
1316
1317The system is left in the same state as when entering BL31 in the default boot
1318flow. In particular:
1319
1320- Running in EL3;
1321- Current state is AArch64;
1322- Little-endian data access;
1323- All exceptions disabled;
1324- MMU disabled;
1325- Caches disabled.
1326
1327Booting an EL3 payload
1328~~~~~~~~~~~~~~~~~~~~~~
1329
1330The EL3 payload image is a standalone image and is not part of the FIP. It is
1331not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios:
1332
1333- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1334 place. In this case, booting it is just a matter of specifying the right
1335 address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF.
1336
1337- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1338 run-time.
1339
1340To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1341used. The infinite loop that it introduces in BL1 stops execution at the right
1342moment for a debugger to take control of the target and load the payload (for
1343example, over JTAG).
1344
1345It is expected that this loading method will work in most cases, as a debugger
1346connection is usually available in a pre-production system. The user is free to
1347use any other platform-specific mechanism to load the EL3 payload, though.
1348
1349Booting an EL3 payload on FVP
1350^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1351
1352The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1353the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1354is undefined on the FVP platform and the FVP platform code doesn't clear it.
1355Therefore, one must modify the way the model is normally invoked in order to
1356clear the mailbox at start-up.
1357
1358One way to do that is to create an 8-byte file containing all zero bytes using
1359the following command:
1360
1361::
1362
1363 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1364
1365and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1366using the following model parameters:
1367
1368::
1369
1370 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1371 --data=mailbox.dat@0x04000000 [Foundation FVP]
1372
1373To provide the model with the EL3 payload image, the following methods may be
1374used:
1375
1376#. If the EL3 payload is able to execute in place, it may be programmed into
1377 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1378 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1379 used for the FIP):
1380
1381 ::
1382
1383 -C bp.flashloader1.fname="/path/to/el3-payload"
1384
1385 On Foundation FVP, there is no flash loader component and the EL3 payload
1386 may be programmed anywhere in flash using method 3 below.
1387
1388#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1389 command may be used to load the EL3 payload ELF image over JTAG:
1390
1391 ::
1392
1393 load /path/to/el3-payload.elf
1394
1395#. The EL3 payload may be pre-loaded in volatile memory using the following
1396 model parameters:
1397
1398 ::
1399
1400 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1401 --data="/path/to/el3-payload"@address [Foundation FVP]
1402
1403 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1404 used when building the Trusted Firmware.
1405
1406Booting an EL3 payload on Juno
1407^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1408
1409If the EL3 payload is able to execute in place, it may be programmed in flash
1410memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1411on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1412Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1413programming" for more information.
1414
1415Alternatively, the same DS-5 command mentioned in the FVP section above can
1416be used to load the EL3 payload's ELF file over JTAG on Juno.
1417
1418Preloaded BL33 alternative boot flow
1419------------------------------------
1420
1421Some platforms have the ability to preload BL33 into memory instead of relying
1422on Trusted Firmware to load it. This may simplify packaging of the normal world
1423code and improve performance in a development environment. When secure world
1424cold boot is complete, Trusted Firmware simply jumps to a BL33 base address
1425provided at build time.
1426
1427For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1428used when compiling the Trusted Firmware. For example, the following command
1429will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at
1430address 0x80000000:
1431
1432::
1433
1434 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1435
1436Boot of a preloaded bootwrapped kernel image on Base FVP
1437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1438
1439The following example uses the AArch64 boot wrapper. This simplifies normal
1440world booting while also making use of TF features. It can be obtained from its
1441repository with:
1442
1443::
1444
1445 git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
1446
1447After compiling it, an ELF file is generated. It can be loaded with the
1448following command:
1449
1450::
1451
1452 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1453 -C bp.secureflashloader.fname=bl1.bin \
1454 -C bp.flashloader0.fname=fip.bin \
1455 -a cluster0.cpu0=<bootwrapped-kernel.elf> \
1456 --start cluster0.cpu0=0x0
1457
1458The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It
1459also sets the PC register to the ELF entry point address, which is not the
1460desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back
1461to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define
1462used when compiling the FIP must match the ELF entry point.
1463
1464Boot of a preloaded bootwrapped kernel image on Juno
1465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1466
1467The procedure to obtain and compile the boot wrapper is very similar to the case
1468of the FVP. The execution must be stopped at the end of bl2\_main(), and the
1469loading method explained above in the EL3 payload boot flow section may be used
1470to load the ELF file over JTAG on Juno.
1471
1472Running the software on FVP
1473---------------------------
1474
1475The latest version of the AArch64 build of ARM Trusted Firmware has been tested
1476on the following ARM FVPs (64-bit host machine only).
1477
David Cunado82509be2017-12-19 16:33:25 +00001478NOTE: Unless otherwise stated, the model version is Version 11.2 Build 11.2.33.
David Cunado124415e2017-06-27 17:31:12 +01001479
1480- ``Foundation_Platform``
David Cunado82509be2017-12-19 16:33:25 +00001481- ``FVP_Base_AEMv8A-AEMv8A`` (Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001482- ``FVP_Base_Cortex-A35x4``
1483- ``FVP_Base_Cortex-A53x4``
1484- ``FVP_Base_Cortex-A57x4-A53x4``
1485- ``FVP_Base_Cortex-A57x4``
1486- ``FVP_Base_Cortex-A72x4-A53x4``
1487- ``FVP_Base_Cortex-A72x4``
1488- ``FVP_Base_Cortex-A73x4-A53x4``
1489- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001490
1491The latest version of the AArch32 build of ARM Trusted Firmware has been tested
1492on the following ARM FVPs (64-bit host machine only).
1493
David Cunado82509be2017-12-19 16:33:25 +00001494- ``FVP_Base_AEMv8A-AEMv8A`` (Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001495- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001496
1497NOTE: The build numbers quoted above are those reported by launching the FVP
1498with the ``--version`` parameter.
1499
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001500NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1501file systems that can be downloaded separately. To run an FVP with a virtio
1502file system image an additional FVP configuration option
1503``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1504used.
1505
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001506NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1507The commands below would report an ``unhandled argument`` error in this case.
1508
1509NOTE: FVPs can be launched with ``--cadi-server`` option such that a
1510CADI-compliant debugger (for example, ARM DS-5) can connect to and control its
1511execution.
1512
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001513NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001514the internal synchronisation timings changed compared to older versions of the
1515models. The models can be launched with ``-Q 100`` option if they are required
1516to match the run time characteristics of the older versions.
1517
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001518The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1519downloaded for free from `ARM's website`_.
1520
David Cunado124415e2017-06-27 17:31:12 +01001521The Cortex-A models listed above are also available to download from
1522`ARM's website`_.
1523
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001524Please refer to the FVP documentation for a detailed description of the model
1525parameter options. A brief description of the important ones that affect the ARM
1526Trusted Firmware and normal world software behavior is provided below.
1527
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001528Obtaining the Flattened Device Trees
1529~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1530
1531Depending on the FVP configuration and Linux configuration used, different
1532FDT files are required. FDTs for the Foundation and Base FVPs can be found in
1533the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a
1534subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
1535and MMC support, and has only one CPU cluster.
1536
1537Note: It is not recommended to use the FDTs built along the kernel because not
1538all FDTs are available from there.
1539
1540- ``fvp-base-gicv2-psci.dtb``
1541
1542 For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
1543 Base memory map configuration.
1544
1545- ``fvp-base-gicv2-psci-aarch32.dtb``
1546
1547 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1548 with Base memory map configuration.
1549
1550- ``fvp-base-gicv3-psci.dtb``
1551
1552 (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
1553 memory map configuration and Linux GICv3 support.
1554
1555- ``fvp-base-gicv3-psci-aarch32.dtb``
1556
1557 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1558 with Base memory map configuration and Linux GICv3 support.
1559
1560- ``fvp-foundation-gicv2-psci.dtb``
1561
1562 For use with Foundation FVP with Base memory map configuration.
1563
1564- ``fvp-foundation-gicv3-psci.dtb``
1565
1566 (Default) For use with Foundation FVP with Base memory map configuration
1567 and Linux GICv3 support.
1568
1569Running on the Foundation FVP with reset to BL1 entrypoint
1570~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1571
1572The following ``Foundation_Platform`` parameters should be used to boot Linux with
15734 CPUs using the AArch64 build of ARM Trusted Firmware.
1574
1575::
1576
1577 <path-to>/Foundation_Platform \
1578 --cores=4 \
1579 --secure-memory \
1580 --visualization \
1581 --gicv3 \
1582 --data="<path-to>/<bl1-binary>"@0x0 \
1583 --data="<path-to>/<FIP-binary>"@0x08000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001584 --data="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001585 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001586 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001587
1588Notes:
1589
1590- BL1 is loaded at the start of the Trusted ROM.
1591- The Firmware Image Package is loaded at the start of NOR FLASH0.
1592- The Linux kernel image and device tree are loaded in DRAM.
1593- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1594 and enable the GICv3 device in the model. Note that without this option,
1595 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1596 is not supported by ARM Trusted Firmware.
1597
1598Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1599~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1600
1601The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1602with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1603
1604::
1605
1606 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1607 -C pctl.startup=0.0.0.0 \
1608 -C bp.secure_memory=1 \
1609 -C bp.tzc_400.diagnostics=1 \
1610 -C cluster0.NUM_CORES=4 \
1611 -C cluster1.NUM_CORES=4 \
1612 -C cache_state_modelled=1 \
1613 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1614 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001615 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001617 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001618
1619Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1620~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1621
1622The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1623with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1624
1625::
1626
1627 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1628 -C pctl.startup=0.0.0.0 \
1629 -C bp.secure_memory=1 \
1630 -C bp.tzc_400.diagnostics=1 \
1631 -C cluster0.NUM_CORES=4 \
1632 -C cluster1.NUM_CORES=4 \
1633 -C cache_state_modelled=1 \
1634 -C cluster0.cpu0.CONFIG64=0 \
1635 -C cluster0.cpu1.CONFIG64=0 \
1636 -C cluster0.cpu2.CONFIG64=0 \
1637 -C cluster0.cpu3.CONFIG64=0 \
1638 -C cluster1.cpu0.CONFIG64=0 \
1639 -C cluster1.cpu1.CONFIG64=0 \
1640 -C cluster1.cpu2.CONFIG64=0 \
1641 -C cluster1.cpu3.CONFIG64=0 \
1642 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1643 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001644 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001645 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001646 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001647
1648Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1649~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1650
1651The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1652boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1653
1654::
1655
1656 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1657 -C pctl.startup=0.0.0.0 \
1658 -C bp.secure_memory=1 \
1659 -C bp.tzc_400.diagnostics=1 \
1660 -C cache_state_modelled=1 \
1661 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1662 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001663 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001664 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001665 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001666
1667Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1668~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1669
1670The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1671boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1672
1673::
1674
1675 <path-to>/FVP_Base_Cortex-A32x4 \
1676 -C pctl.startup=0.0.0.0 \
1677 -C bp.secure_memory=1 \
1678 -C bp.tzc_400.diagnostics=1 \
1679 -C cache_state_modelled=1 \
1680 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1681 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001682 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001684 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001685
1686Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1687~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1688
1689The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1690with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1691
1692::
1693
1694 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1695 -C pctl.startup=0.0.0.0 \
1696 -C bp.secure_memory=1 \
1697 -C bp.tzc_400.diagnostics=1 \
1698 -C cluster0.NUM_CORES=4 \
1699 -C cluster1.NUM_CORES=4 \
1700 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001701 -C cluster0.cpu0.RVBAR=0x04020000 \
1702 -C cluster0.cpu1.RVBAR=0x04020000 \
1703 -C cluster0.cpu2.RVBAR=0x04020000 \
1704 -C cluster0.cpu3.RVBAR=0x04020000 \
1705 -C cluster1.cpu0.RVBAR=0x04020000 \
1706 -C cluster1.cpu1.RVBAR=0x04020000 \
1707 -C cluster1.cpu2.RVBAR=0x04020000 \
1708 -C cluster1.cpu3.RVBAR=0x04020000 \
1709 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001710 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1711 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001712 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001714 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001715
1716Notes:
1717
1718- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1719 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1720 parameter is needed to load the individual bootloader images in memory.
1721 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
1722 Payload.
1723
1724- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1725 X and Y are the cluster and CPU numbers respectively, is used to set the
1726 reset vector for each core.
1727
1728- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1729 changing the value of
1730 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1731 ``BL32_BASE``.
1732
1733Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1734~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1735
1736The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1737with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1738
1739::
1740
1741 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1742 -C pctl.startup=0.0.0.0 \
1743 -C bp.secure_memory=1 \
1744 -C bp.tzc_400.diagnostics=1 \
1745 -C cluster0.NUM_CORES=4 \
1746 -C cluster1.NUM_CORES=4 \
1747 -C cache_state_modelled=1 \
1748 -C cluster0.cpu0.CONFIG64=0 \
1749 -C cluster0.cpu1.CONFIG64=0 \
1750 -C cluster0.cpu2.CONFIG64=0 \
1751 -C cluster0.cpu3.CONFIG64=0 \
1752 -C cluster1.cpu0.CONFIG64=0 \
1753 -C cluster1.cpu1.CONFIG64=0 \
1754 -C cluster1.cpu2.CONFIG64=0 \
1755 -C cluster1.cpu3.CONFIG64=0 \
1756 -C cluster0.cpu0.RVBAR=0x04001000 \
1757 -C cluster0.cpu1.RVBAR=0x04001000 \
1758 -C cluster0.cpu2.RVBAR=0x04001000 \
1759 -C cluster0.cpu3.RVBAR=0x04001000 \
1760 -C cluster1.cpu0.RVBAR=0x04001000 \
1761 -C cluster1.cpu1.RVBAR=0x04001000 \
1762 -C cluster1.cpu2.RVBAR=0x04001000 \
1763 -C cluster1.cpu3.RVBAR=0x04001000 \
1764 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1765 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001766 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001767 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001768 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001769
1770Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1771It should match the address programmed into the RVBAR register as well.
1772
1773Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1774~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1775
1776The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1777boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1778
1779::
1780
1781 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1782 -C pctl.startup=0.0.0.0 \
1783 -C bp.secure_memory=1 \
1784 -C bp.tzc_400.diagnostics=1 \
1785 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001786 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1787 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1788 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1789 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1790 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1791 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1792 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1793 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1794 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001795 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1796 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001797 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001798 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001799 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001800
1801Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1802~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1803
1804The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1805boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1806
1807::
1808
1809 <path-to>/FVP_Base_Cortex-A32x4 \
1810 -C pctl.startup=0.0.0.0 \
1811 -C bp.secure_memory=1 \
1812 -C bp.tzc_400.diagnostics=1 \
1813 -C cache_state_modelled=1 \
1814 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1815 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1816 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1817 -C cluster0.cpu3.RVBARADDR=0x04001000 \
1818 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1819 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001820 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001821 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001822 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001823
1824Running the software on Juno
1825----------------------------
1826
David Cunadob2de0992017-06-29 12:01:33 +01001827This version of the ARM Trusted Firmware has been tested on variants r0, r1 and
1828r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001829
1830To execute the software stack on Juno, the version of the Juno board recovery
1831image indicated in the `Linaro Release Notes`_ must be installed. If you have an
1832earlier version installed or are unsure which version is installed, please
1833re-install the recovery image by following the
1834`Instructions for using Linaro's deliverables on Juno`_.
1835
1836Preparing Trusted Firmware images
1837~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1838
1839After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying
1840to the ``SOFTWARE/`` directory of the Juno SD card.
1841
1842Other Juno software information
1843~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1844
1845Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno
1846software information. Please also refer to the `Juno Getting Started Guide`_ to
1847get more detailed information about the Juno ARM development platform and how to
1848configure it.
1849
1850Testing SYSTEM SUSPEND on Juno
1851~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1852
1853The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
1854to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
1855on Juno, at the linux shell prompt, issue the following command:
1856
1857::
1858
1859 echo +10 > /sys/class/rtc/rtc0/wakealarm
1860 echo -n mem > /sys/power/state
1861
1862The Juno board should suspend to RAM and then wakeup after 10 seconds due to
1863wakeup interrupt from RTC.
1864
1865--------------
1866
1867*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
1868
David Cunadob2de0992017-06-29 12:01:33 +01001869.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001870.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00001871.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
1872.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes#1710
1873.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
1874.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001875.. _ARM Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001876.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01001877.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001878.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001879.. _Trusted Board Boot: trusted-board-boot.rst
1880.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001881.. _Firmware Update: firmware-update.rst
1882.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001883.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
1884.. _mbed TLS Security Center: https://tls.mbed.org/security
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001885.. _ARM's website: `FVP models`_
1886.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001887.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01001888.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf