| Madhukar Pappireddy | 0cb58bc | 2024-06-17 15:12:26 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2022, Google LLC. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef SIMD_CTX_H |
| 9 | #define SIMD_CTX_H |
| 10 | |
| 11 | /******************************************************************************* |
| 12 | * Constants that allow assembler code to access members of and the 'simd_context' |
| 13 | * structure at their correct offsets. |
| 14 | ******************************************************************************/ |
| 15 | |
| 16 | #if CTX_INCLUDE_FPREGS |
| 17 | |
| 18 | #define SIMD_VECTOR_LEN_BYTES U(16) /* 128 bits fixed vector length for FPU */ |
| 19 | |
| 20 | #define CTX_SIMD_VECTORS U(0) |
| 21 | /* there are 32 vector registers, each of size SIMD_VECTOR_LEN_BYTES */ |
| 22 | #define CTX_SIMD_FPSR (CTX_SIMD_VECTORS + (32 * SIMD_VECTOR_LEN_BYTES)) |
| 23 | #define CTX_SIMD_FPCR (CTX_SIMD_FPSR + 8) |
| 24 | |
| 25 | #if CTX_INCLUDE_AARCH32_REGS |
| 26 | #define CTX_SIMD_FPEXC32 (CTX_SIMD_FPCR + 8) |
| 27 | #endif /* CTX_INCLUDE_AARCH32_REGS */ |
| 28 | |
| 29 | #ifndef __ASSEMBLER__ |
| 30 | |
| 31 | #include <stdint.h> |
| 32 | #include <lib/cassert.h> |
| 33 | |
| 34 | /* |
| 35 | * Please don't change order of fields in this struct as that may violate |
| 36 | * alignment requirements and affect how assembly code accesses members of this |
| 37 | * struct. |
| 38 | */ |
| 39 | typedef struct { |
| 40 | uint8_t vectors[32][SIMD_VECTOR_LEN_BYTES]; |
| 41 | uint8_t fpsr[8]; |
| 42 | uint8_t fpcr[8]; |
| 43 | #if CTX_INCLUDE_FPREGS && CTX_INCLUDE_AARCH32_REGS |
| 44 | /* 16 bytes to align to next 16 byte boundary */ |
| 45 | uint8_t fpexc32_el2[16]; |
| 46 | #endif |
| 47 | } simd_regs_t __attribute__((aligned(16))); |
| 48 | |
| 49 | CASSERT(CTX_SIMD_VECTORS == __builtin_offsetof(simd_regs_t, vectors), |
| 50 | assert_vectors_mismatch); |
| 51 | |
| 52 | CASSERT(CTX_SIMD_FPSR == __builtin_offsetof(simd_regs_t, fpsr), |
| 53 | assert_fpsr_mismatch); |
| 54 | |
| 55 | CASSERT(CTX_SIMD_FPCR == __builtin_offsetof(simd_regs_t, fpcr), |
| 56 | assert_fpcr_mismatch); |
| 57 | |
| 58 | #if CTX_INCLUDE_FPREGS && CTX_INCLUDE_AARCH32_REGS |
| 59 | CASSERT(CTX_SIMD_FPEXC32 == __builtin_offsetof(simd_regs_t, fpexc32_el2), |
| 60 | assert_fpex32_mismtatch); |
| 61 | #endif |
| 62 | |
| 63 | void simd_ctx_save(uint32_t security_state, bool hint_sve); |
| 64 | void simd_ctx_restore(uint32_t security_state); |
| 65 | |
| 66 | #endif /* __ASSEMBLER__ */ |
| 67 | |
| 68 | #endif /* CTX_INCLUDE_FPREGS */ |
| 69 | |
| 70 | #endif /* SIMD_CTX_H */ |