Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 35 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 36 | #include <platform.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | #include <platform_def.h> |
Dan Handley | bcd60ba | 2014-04-17 18:53:42 +0100 | [diff] [blame] | 38 | #include "bl1_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 41 | * Runs BL2 from the given entry point. It results in dropping the |
| 42 | * exception level |
| 43 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 44 | static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep) |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 45 | { |
| 46 | bl1_arch_next_el_setup(); |
| 47 | |
| 48 | /* Tell next EL what we want done */ |
| 49 | bl2_ep->args.arg0 = RUN_IMAGE; |
| 50 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 51 | if (GET_SECURITY_STATE(bl2_ep->h.attr) == NON_SECURE) |
| 52 | change_security_state(GET_SECURITY_STATE(bl2_ep->h.attr)); |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 53 | |
| 54 | write_spsr_el3(bl2_ep->spsr); |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 55 | write_elr_el3(bl2_ep->pc); |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 56 | |
| 57 | eret(bl2_ep->args.arg0, |
| 58 | bl2_ep->args.arg1, |
| 59 | bl2_ep->args.arg2, |
| 60 | bl2_ep->args.arg3, |
| 61 | bl2_ep->args.arg4, |
| 62 | bl2_ep->args.arg5, |
| 63 | bl2_ep->args.arg6, |
| 64 | bl2_ep->args.arg7); |
| 65 | } |
| 66 | |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 67 | /******************************************************************************* |
| 68 | * The next function has a weak definition. Platform specific code can override |
| 69 | * it if it wishes to. |
| 70 | ******************************************************************************/ |
| 71 | #pragma weak bl1_init_bl2_mem_layout |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 72 | |
| 73 | /******************************************************************************* |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 74 | * Function that takes a memory layout into which BL2 has been loaded and |
| 75 | * populates a new memory layout for BL2 that ensures that BL1's data sections |
| 76 | * resident in secure RAM are not visible to BL2. |
| 77 | ******************************************************************************/ |
| 78 | void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, |
| 79 | meminfo_t *bl2_mem_layout) |
| 80 | { |
| 81 | const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; |
| 82 | |
| 83 | assert(bl1_mem_layout != NULL); |
| 84 | assert(bl2_mem_layout != NULL); |
| 85 | |
| 86 | /* Check that BL1's memory is lying outside of the free memory */ |
| 87 | assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || |
| 88 | (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size)); |
| 89 | |
| 90 | /* Remove BL1 RW data from the scope of memory visible to BL2 */ |
| 91 | *bl2_mem_layout = *bl1_mem_layout; |
| 92 | reserve_mem(&bl2_mem_layout->total_base, |
| 93 | &bl2_mem_layout->total_size, |
| 94 | BL1_RAM_BASE, |
| 95 | bl1_size); |
| 96 | |
| 97 | flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); |
| 98 | } |
| 99 | |
| 100 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | * Function to perform late architectural and platform specific initialization. |
| 102 | * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only |
| 103 | * called by the primary cpu after a cold boot. |
| 104 | * TODO: Add support for alternative image load mechanism e.g using virtio/elf |
| 105 | * loader etc. |
| 106 | ******************************************************************************/ |
| 107 | void bl1_main(void) |
| 108 | { |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 109 | #if DEBUG |
Vikram Kanigiri | 78a6e0c | 2014-03-11 17:41:00 +0000 | [diff] [blame] | 110 | unsigned long sctlr_el3 = read_sctlr_el3(); |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 111 | #endif |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 112 | image_info_t bl2_image_info = { {0} }; |
| 113 | entry_point_info_t bl2_ep = { {0} }; |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 114 | meminfo_t *bl1_tzram_layout; |
| 115 | meminfo_t *bl2_tzram_layout = 0x0; |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 116 | int err; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 117 | |
| 118 | /* |
| 119 | * Ensure that MMU/Caches and coherency are turned on |
| 120 | */ |
| 121 | assert(sctlr_el3 | SCTLR_M_BIT); |
| 122 | assert(sctlr_el3 | SCTLR_C_BIT); |
| 123 | assert(sctlr_el3 | SCTLR_I_BIT); |
| 124 | |
| 125 | /* Perform remaining generic architectural setup from EL3 */ |
| 126 | bl1_arch_setup(); |
| 127 | |
| 128 | /* Perform platform setup in BL1. */ |
| 129 | bl1_platform_setup(); |
| 130 | |
| 131 | /* Announce our arrival */ |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 132 | tf_printf(FIRMWARE_WELCOME_STR); |
Juan Castillo | 04be3a5 | 2014-06-30 11:41:46 +0100 | [diff] [blame] | 133 | tf_printf("%s\n", version_string); |
| 134 | tf_printf("%s\n", build_message); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 135 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 136 | SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); |
| 137 | SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0); |
| 138 | |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 139 | /* Find out how much free trusted ram remains after BL1 load */ |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 140 | bl1_tzram_layout = bl1_plat_sec_mem_layout(); |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 141 | |
| 142 | /* Load the BL2 image */ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 143 | err = load_image(bl1_tzram_layout, |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 144 | BL2_IMAGE_NAME, |
| 145 | BL2_BASE, |
| 146 | &bl2_image_info, |
| 147 | &bl2_ep); |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 148 | if (err) { |
| 149 | /* |
| 150 | * TODO: print failure to load BL2 but also add a tzwdog timer |
| 151 | * which will reset the system eventually. |
| 152 | */ |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 153 | tf_printf("Failed to load boot loader stage 2 (BL2) firmware.\n"); |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 154 | panic(); |
| 155 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 156 | /* |
| 157 | * Create a new layout of memory for BL2 as seen by BL1 i.e. |
| 158 | * tell it the amount of total and free memory available. |
| 159 | * This layout is created at the first free address visible |
| 160 | * to BL2. BL2 will read the memory layout before using its |
| 161 | * memory for other purposes. |
| 162 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 163 | bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 164 | bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 165 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 166 | bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep); |
| 167 | bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout; |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 168 | tf_printf("Booting trusted firmware boot loader stage 2\n"); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | #if DEBUG |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 170 | tf_printf("BL2 address = 0x%llx\n", |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 171 | (unsigned long long) bl2_ep.pc); |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 172 | tf_printf("BL2 cpsr = 0x%x\n", bl2_ep.spsr); |
| 173 | tf_printf("BL2 memory layout address = 0x%llx\n", |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 174 | (unsigned long long) bl2_tzram_layout); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 175 | #endif |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 176 | bl1_run_bl2(&bl2_ep); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 178 | return; |
| 179 | } |
| 180 | |
| 181 | /******************************************************************************* |
| 182 | * Temporary function to print the fact that BL2 has done its job and BL31 is |
| 183 | * about to be loaded. This is needed as long as printfs cannot be used |
| 184 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 185 | void display_boot_progress(entry_point_info_t *bl31_ep_info) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 186 | { |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 187 | tf_printf("Booting trusted firmware boot loader stage 3\n\r"); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 188 | #if DEBUG |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 189 | tf_printf("BL31 address = 0x%llx\n", (unsigned long long)bl31_ep_info->pc); |
| 190 | tf_printf("BL31 cpsr = 0x%llx\n", (unsigned long long)bl31_ep_info->spsr); |
| 191 | tf_printf("BL31 params address = 0x%llx\n", |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 192 | (unsigned long long)bl31_ep_info->args.arg0); |
Soby Mathew | afe7e2f | 2014-06-12 17:23:58 +0100 | [diff] [blame] | 193 | tf_printf("BL31 plat params address = 0x%llx\n", |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 194 | (unsigned long long)bl31_ep_info->args.arg1); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 195 | #endif |
| 196 | return; |
| 197 | } |