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Varun Wadekar0f3baa02015-07-16 11:36:33 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
37 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
38 * call as the `state-id` field in the 'power state' parameter.
39 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +053040#define PSTATE_ID_SOC_POWERDN 0xD
Varun Wadekar0f3baa02015-07-16 11:36:33 +053041
42/*******************************************************************************
43 * GIC memory map
44 ******************************************************************************/
45#define TEGRA_GICD_BASE 0x50041000
46#define TEGRA_GICC_BASE 0x50042000
47
48/*******************************************************************************
49 * Tegra micro-seconds timer constants
50 ******************************************************************************/
51#define TEGRA_TMRUS_BASE 0x60005010
52
53/*******************************************************************************
54 * Tegra Clock and Reset Controller constants
55 ******************************************************************************/
56#define TEGRA_CAR_RESET_BASE 0x60006000
57
58/*******************************************************************************
59 * Tegra Flow Controller constants
60 ******************************************************************************/
61#define TEGRA_FLOWCTRL_BASE 0x60007000
62
63/*******************************************************************************
64 * Tegra Secure Boot Controller constants
65 ******************************************************************************/
66#define TEGRA_SB_BASE 0x6000C200
67
68/*******************************************************************************
69 * Tegra Exception Vectors constants
70 ******************************************************************************/
71#define TEGRA_EVP_BASE 0x6000F000
72
73/*******************************************************************************
74 * Tegra Power Mgmt Controller constants
75 ******************************************************************************/
76#define TEGRA_PMC_BASE 0x7000E400
77
78/*******************************************************************************
79 * Tegra Memory Controller constants
80 ******************************************************************************/
81#define TEGRA_MC_BASE 0x70019000
82
83#endif /* __TEGRA_DEF_H__ */