Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 0c603d18a5668fa0c100368309b319346f19184c / . / plat / nvidia / tegra / include / platform_def.h
blob: 2a7935fd086ccb4728e052445102a0520ff47205 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#include <arch.h>
35#include <common_def.h>
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]36#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]37
38/*******************************************************************************
39 * Generic platform constants
40 ******************************************************************************/
41
42/* Size of cacheable stacks */
43#if DEBUG_XLAT_TABLE
44#define PLATFORM_STACK_SIZE 0x800
45#elif IMAGE_BL31
46#define PLATFORM_STACK_SIZE 0x400
47#endif
48
49#define TEGRA_PRIMARY_CPU 0x0
50
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]51#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]52#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
53 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]54#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]55 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]56
57/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]58 * Platform power states
59 ******************************************************************************/
60#define PLAT_MAX_RET_STATE 1
61#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
62
63/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]64 * Platform console related constants
65 ******************************************************************************/
66#define TEGRA_CONSOLE_BAUDRATE 115200
67#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000
68
69/*******************************************************************************
70 * Platform memory map related constants
71 ******************************************************************************/
72/* Size of trusted dram */
73#define TZDRAM_SIZE 0x00400000
74#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
75
76/*******************************************************************************
77 * BL31 specific defines.
78 ******************************************************************************/
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]79#define BL31_SIZE 0x20000
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]80#define BL31_BASE TZDRAM_BASE
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]81#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
82#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
83#define BL32_LIMIT TZDRAM_END
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]84
85/*******************************************************************************
86 * Platform specific page table and MMU setup constants
87 ******************************************************************************/
88#define ADDR_SPACE_SIZE (1ull << 32)
89#define MAX_XLAT_TABLES 3
90#define MAX_MMAP_REGIONS 8
91
92/*******************************************************************************
93 * Some data must be aligned on the biggest cache line size in the platform.
94 * This is known only to the platform as it might have a combination of
95 * integrated and external caches.
96 ******************************************************************************/
97#define CACHE_WRITEBACK_SHIFT 6
98#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
99
100#endif /* __PLATFORM_DEF_H__ */