Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 1 | /* |
Pranav Madhu | 0c02e81 | 2021-12-11 22:23:25 +0530 | [diff] [blame^] | 2 | * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <string.h> |
| 9 | |
| 10 | #include <arch_helpers.h> |
| 11 | #include <common/debug.h> |
Antonio Nino Diaz | 326f56b | 2019-01-23 18:55:03 +0000 | [diff] [blame] | 12 | #include <drivers/arm/css/css_scp.h> |
Antonio Nino Diaz | c30db5b | 2019-01-23 20:37:32 +0000 | [diff] [blame] | 13 | #include <drivers/arm/css/scmi.h> |
Pranav Madhu | 0c02e81 | 2021-12-11 22:23:25 +0530 | [diff] [blame^] | 14 | #include <lib/mmio.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 15 | #include <plat/arm/common/plat_arm.h> |
| 16 | #include <plat/arm/css/common/css_pm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <plat/common/platform.h> |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 18 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 20 | /* |
| 21 | * This file implements the SCP helper functions using SCMI protocol. |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * SCMI power state parameter bit field encoding for ARM CSS platforms. |
| 26 | * |
| 27 | * 31 20 19 16 15 12 11 8 7 4 3 0 |
| 28 | * +-------------------------------------------------------------+ |
| 29 | * | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 | |
| 30 | * | | | state | state | state | state | |
| 31 | * +-------------------------------------------------------------+ |
| 32 | * |
| 33 | * `Max level` encodes the highest level that has a valid power state |
| 34 | * encoded in the power state. |
| 35 | */ |
| 36 | #define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16 |
| 37 | #define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4 |
| 38 | #define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \ |
| 39 | ((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1) |
Daniel Boulby | ddf6d40 | 2018-05-09 12:21:46 +0100 | [diff] [blame] | 40 | #define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \ |
| 41 | (_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\ |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 42 | << SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT |
Daniel Boulby | ddf6d40 | 2018-05-09 12:21:46 +0100 | [diff] [blame] | 43 | #define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \ |
| 44 | (((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \ |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 45 | & SCMI_PWR_STATE_MAX_PWR_LVL_MASK) |
| 46 | |
| 47 | #define SCMI_PWR_STATE_LVL_WIDTH 4 |
| 48 | #define SCMI_PWR_STATE_LVL_MASK \ |
| 49 | ((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1) |
Daniel Boulby | ddf6d40 | 2018-05-09 12:21:46 +0100 | [diff] [blame] | 50 | #define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \ |
| 51 | (_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \ |
| 52 | << (SCMI_PWR_STATE_LVL_WIDTH * (_level)) |
| 53 | #define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \ |
| 54 | (((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \ |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 55 | SCMI_PWR_STATE_LVL_MASK) |
| 56 | |
| 57 | /* |
| 58 | * The SCMI power state enumeration for a power domain level |
| 59 | */ |
| 60 | typedef enum { |
| 61 | scmi_power_state_off = 0, |
| 62 | scmi_power_state_on = 1, |
| 63 | scmi_power_state_sleep = 2, |
| 64 | } scmi_power_state_t; |
| 65 | |
| 66 | /* |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 67 | * The global handles for invoking the SCMI driver APIs after the driver |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 68 | * has been initialized. |
| 69 | */ |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 70 | static void *scmi_handles[PLAT_ARM_SCMI_CHANNEL_COUNT]; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 71 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 72 | /* The global SCMI channels array */ |
| 73 | static scmi_channel_t scmi_channels[PLAT_ARM_SCMI_CHANNEL_COUNT]; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 74 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 75 | /* |
| 76 | * Channel ID for the default SCMI channel. |
| 77 | * The default channel is used to issue SYSTEM level SCMI requests and is |
| 78 | * initialized to the channel which has the boot cpu as its resource. |
| 79 | */ |
| 80 | static uint32_t default_scmi_channel_id; |
| 81 | |
| 82 | /* |
| 83 | * TODO: Allow use of channel specific lock instead of using a single lock for |
| 84 | * all the channels. |
| 85 | */ |
Roberto Vargas | 0099694 | 2017-11-13 13:41:58 +0000 | [diff] [blame] | 86 | ARM_SCMI_INSTANTIATE_LOCK; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 87 | |
| 88 | /* |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 89 | * Function to obtain the SCMI Domain ID and SCMI Channel number from the linear |
| 90 | * core position. The SCMI Channel number is encoded in the upper 16 bits and |
| 91 | * the Domain ID is encoded in the lower 16 bits in each entry of the mapping |
| 92 | * array exported by the platform. |
| 93 | */ |
| 94 | static void css_scp_core_pos_to_scmi_channel(unsigned int core_pos, |
| 95 | unsigned int *scmi_domain_id, unsigned int *scmi_channel_id) |
| 96 | { |
| 97 | unsigned int composite_id; |
| 98 | |
| 99 | composite_id = plat_css_core_pos_to_scmi_dmn_id_map[core_pos]; |
| 100 | |
| 101 | *scmi_channel_id = GET_SCMI_CHANNEL_ID(composite_id); |
| 102 | *scmi_domain_id = GET_SCMI_DOMAIN_ID(composite_id); |
| 103 | } |
| 104 | |
| 105 | /* |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 106 | * Helper function to suspend a CPU power domain and its parent power domains |
| 107 | * if applicable. |
| 108 | */ |
Roberto Vargas | 5f5a5e6 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 109 | void css_scp_suspend(const struct psci_power_state *target_state) |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 110 | { |
Deepak Pandey | 207c522 | 2017-10-10 21:34:32 +0530 | [diff] [blame] | 111 | int ret; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 112 | |
| 113 | /* At least power domain level 0 should be specified to be suspended */ |
| 114 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 115 | ARM_LOCAL_STATE_OFF); |
| 116 | |
| 117 | /* Check if power down at system power domain level is requested */ |
Nariman Poushin | cd95626 | 2018-05-01 09:28:40 +0100 | [diff] [blame] | 118 | if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 119 | /* Issue SCMI command for SYSTEM_SUSPEND on all SCMI channels */ |
| 120 | ret = scmi_sys_pwr_state_set( |
| 121 | scmi_handles[default_scmi_channel_id], |
| 122 | SCMI_SYS_PWR_FORCEFUL_REQ, SCMI_SYS_PWR_SUSPEND); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 123 | if (ret != SCMI_E_SUCCESS) { |
| 124 | ERROR("SCMI system power domain suspend return 0x%x unexpected\n", |
| 125 | ret); |
| 126 | panic(); |
| 127 | } |
| 128 | return; |
| 129 | } |
Deepak Pandey | 207c522 | 2017-10-10 21:34:32 +0530 | [diff] [blame] | 130 | #if !HW_ASSISTED_COHERENCY |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 131 | unsigned int lvl, channel_id, domain_id; |
Deepak Pandey | 207c522 | 2017-10-10 21:34:32 +0530 | [diff] [blame] | 132 | uint32_t scmi_pwr_state = 0; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 133 | /* |
| 134 | * If we reach here, then assert that power down at system power domain |
| 135 | * level is running. |
| 136 | */ |
Soby Mathew | fd2e5e4 | 2018-09-10 11:32:49 +0100 | [diff] [blame] | 137 | assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 138 | |
| 139 | /* For level 0, specify `scmi_power_state_sleep` as the power state */ |
| 140 | SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0, |
| 141 | scmi_power_state_sleep); |
| 142 | |
| 143 | for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { |
| 144 | if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) |
| 145 | break; |
| 146 | |
| 147 | assert(target_state->pwr_domain_state[lvl] == |
| 148 | ARM_LOCAL_STATE_OFF); |
| 149 | /* |
| 150 | * Specify `scmi_power_state_off` as power state for higher |
| 151 | * levels. |
| 152 | */ |
| 153 | SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
| 154 | scmi_power_state_off); |
| 155 | } |
| 156 | |
| 157 | SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
| 158 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 159 | css_scp_core_pos_to_scmi_channel(plat_my_core_pos(), |
| 160 | &domain_id, &channel_id); |
| 161 | ret = scmi_pwr_state_set(scmi_handles[channel_id], |
| 162 | domain_id, scmi_pwr_state); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 163 | |
| 164 | if (ret != SCMI_E_SUCCESS) { |
| 165 | ERROR("SCMI set power state command return 0x%x unexpected\n", |
| 166 | ret); |
| 167 | panic(); |
| 168 | } |
Deepak Pandey | 207c522 | 2017-10-10 21:34:32 +0530 | [diff] [blame] | 169 | #endif |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* |
| 173 | * Helper function to turn off a CPU power domain and its parent power domains |
| 174 | * if applicable. |
| 175 | */ |
Roberto Vargas | 85664f5 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 176 | void css_scp_off(const struct psci_power_state *target_state) |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 177 | { |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 178 | unsigned int lvl = 0, channel_id, domain_id; |
Ambroise Vincent | a88a35d | 2019-02-14 09:48:21 +0000 | [diff] [blame] | 179 | int ret; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 180 | uint32_t scmi_pwr_state = 0; |
| 181 | |
| 182 | /* At-least the CPU level should be specified to be OFF */ |
| 183 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 184 | ARM_LOCAL_STATE_OFF); |
| 185 | |
| 186 | /* PSCI CPU OFF cannot be used to turn OFF system power domain */ |
Soby Mathew | fd2e5e4 | 2018-09-10 11:32:49 +0100 | [diff] [blame] | 187 | assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 188 | |
| 189 | for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { |
| 190 | if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) |
| 191 | break; |
| 192 | |
| 193 | assert(target_state->pwr_domain_state[lvl] == |
| 194 | ARM_LOCAL_STATE_OFF); |
| 195 | SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
| 196 | scmi_power_state_off); |
| 197 | } |
| 198 | |
| 199 | SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
| 200 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 201 | css_scp_core_pos_to_scmi_channel(plat_my_core_pos(), |
| 202 | &domain_id, &channel_id); |
| 203 | ret = scmi_pwr_state_set(scmi_handles[channel_id], |
| 204 | domain_id, scmi_pwr_state); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 205 | if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { |
| 206 | ERROR("SCMI set power state command return 0x%x unexpected\n", |
| 207 | ret); |
| 208 | panic(); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | /* |
| 213 | * Helper function to turn ON a CPU power domain and its parent power domains |
| 214 | * if applicable. |
| 215 | */ |
| 216 | void css_scp_on(u_register_t mpidr) |
| 217 | { |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 218 | unsigned int lvl = 0, channel_id, core_pos, domain_id; |
| 219 | int ret; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 220 | uint32_t scmi_pwr_state = 0; |
| 221 | |
| 222 | for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) |
| 223 | SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, |
| 224 | scmi_power_state_on); |
| 225 | |
| 226 | SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); |
| 227 | |
Manish Pandey | bb66759 | 2020-03-03 17:12:10 +0000 | [diff] [blame] | 228 | core_pos = (unsigned int)plat_core_pos_by_mpidr(mpidr); |
| 229 | assert(core_pos < PLATFORM_CORE_COUNT); |
Soby Mathew | e089e3f | 2017-06-09 15:04:43 +0100 | [diff] [blame] | 230 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 231 | css_scp_core_pos_to_scmi_channel(core_pos, &domain_id, |
| 232 | &channel_id); |
| 233 | ret = scmi_pwr_state_set(scmi_handles[channel_id], |
| 234 | domain_id, scmi_pwr_state); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 235 | if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { |
| 236 | ERROR("SCMI set power state command return 0x%x unexpected\n", |
| 237 | ret); |
| 238 | panic(); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | /* |
| 243 | * Helper function to get the power state of a power domain node as reported |
| 244 | * by the SCP. |
| 245 | */ |
| 246 | int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) |
| 247 | { |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 248 | int ret; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 249 | uint32_t scmi_pwr_state = 0, lvl_state; |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 250 | unsigned int channel_id, cpu_idx, domain_id; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 251 | |
| 252 | /* We don't support get power state at the system power domain level */ |
| 253 | if ((power_level > PLAT_MAX_PWR_LVL) || |
| 254 | (power_level == CSS_SYSTEM_PWR_DMN_LVL)) { |
| 255 | WARN("Invalid power level %u specified for SCMI get power state\n", |
| 256 | power_level); |
| 257 | return PSCI_E_INVALID_PARAMS; |
| 258 | } |
| 259 | |
Manish Pandey | bb66759 | 2020-03-03 17:12:10 +0000 | [diff] [blame] | 260 | cpu_idx = (unsigned int)plat_core_pos_by_mpidr(mpidr); |
| 261 | assert(cpu_idx < PLATFORM_CORE_COUNT); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 262 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 263 | css_scp_core_pos_to_scmi_channel(cpu_idx, &domain_id, &channel_id); |
| 264 | ret = scmi_pwr_state_get(scmi_handles[channel_id], |
| 265 | domain_id, &scmi_pwr_state); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 266 | |
| 267 | if (ret != SCMI_E_SUCCESS) { |
| 268 | WARN("SCMI get power state command return 0x%x unexpected\n", |
| 269 | ret); |
| 270 | return PSCI_E_INVALID_PARAMS; |
| 271 | } |
| 272 | |
| 273 | /* |
| 274 | * Find the maximum power level described in the get power state |
| 275 | * command. If it is less than the requested power level, then assume |
| 276 | * the requested power level is ON. |
| 277 | */ |
| 278 | if (SCMI_GET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state) < power_level) |
| 279 | return HW_ON; |
| 280 | |
| 281 | lvl_state = SCMI_GET_PWR_STATE_LVL(scmi_pwr_state, power_level); |
| 282 | if (lvl_state == scmi_power_state_on) |
| 283 | return HW_ON; |
| 284 | |
| 285 | assert((lvl_state == scmi_power_state_off) || |
| 286 | (lvl_state == scmi_power_state_sleep)); |
| 287 | return HW_OFF; |
| 288 | } |
| 289 | |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 290 | void __dead2 css_scp_system_off(int state) |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 291 | { |
| 292 | int ret; |
| 293 | |
| 294 | /* |
Pranav Madhu | 0c02e81 | 2021-12-11 22:23:25 +0530 | [diff] [blame^] | 295 | * Before issuing the system power down command, set the trusted mailbox |
| 296 | * to 0. This will ensure that in the case of a warm/cold reset, the |
| 297 | * primary CPU executes from the cold boot sequence. |
| 298 | */ |
| 299 | mmio_write_64(PLAT_ARM_TRUSTED_MAILBOX_BASE, 0U); |
| 300 | |
| 301 | /* |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 302 | * Disable GIC CPU interface to prevent pending interrupt from waking |
| 303 | * up the AP from WFI. |
| 304 | */ |
| 305 | plat_arm_gic_cpuif_disable(); |
| 306 | |
| 307 | /* |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 308 | * Issue SCMI command. First issue a graceful |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 309 | * request and if that fails force the request. |
| 310 | */ |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 311 | ret = scmi_sys_pwr_state_set(scmi_handles[default_scmi_channel_id], |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 312 | SCMI_SYS_PWR_FORCEFUL_REQ, |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 313 | state); |
| 314 | |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 315 | if (ret != SCMI_E_SUCCESS) { |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 316 | ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n", |
| 317 | state, ret); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 318 | panic(); |
| 319 | } |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 320 | wfi(); |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 321 | ERROR("CSS set power state: operation not handled.\n"); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 322 | panic(); |
| 323 | } |
| 324 | |
| 325 | /* |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 326 | * Helper function to shutdown the system via SCMI. |
| 327 | */ |
| 328 | void __dead2 css_scp_sys_shutdown(void) |
| 329 | { |
| 330 | css_scp_system_off(SCMI_SYS_PWR_SHUTDOWN); |
| 331 | } |
| 332 | |
| 333 | /* |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 334 | * Helper function to reset the system via SCMI. |
| 335 | */ |
| 336 | void __dead2 css_scp_sys_reboot(void) |
| 337 | { |
Roberto Vargas | fc2b4eb | 2017-07-31 09:45:10 +0100 | [diff] [blame] | 338 | css_scp_system_off(SCMI_SYS_PWR_COLD_RESET); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 339 | } |
| 340 | |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 341 | static int scmi_ap_core_init(scmi_channel_t *ch) |
| 342 | { |
| 343 | #if PROGRAMMABLE_RESET_ADDRESS |
| 344 | uint32_t version; |
| 345 | int ret; |
| 346 | |
| 347 | ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); |
| 348 | if (ret != SCMI_E_SUCCESS) { |
| 349 | WARN("SCMI AP core protocol version message failed\n"); |
| 350 | return -1; |
| 351 | } |
| 352 | |
| 353 | if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) { |
| 354 | WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n", |
| 355 | version, SCMI_AP_CORE_PROTO_VER); |
| 356 | return -1; |
| 357 | } |
| 358 | INFO("SCMI AP core protocol version 0x%x detected\n", version); |
| 359 | #endif |
| 360 | return 0; |
| 361 | } |
| 362 | |
Daniel Boulby | f45a4bb | 2018-09-18 13:26:03 +0100 | [diff] [blame] | 363 | void __init plat_arm_pwrc_setup(void) |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 364 | { |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 365 | unsigned int composite_id, idx; |
| 366 | |
| 367 | for (idx = 0; idx < PLAT_ARM_SCMI_CHANNEL_COUNT; idx++) { |
Andre Przywara | 42c5cd2 | 2021-10-14 10:36:46 +0100 | [diff] [blame] | 368 | INFO("Initializing SCMI driver on channel %d\n", idx); |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 369 | |
| 370 | scmi_channels[idx].info = plat_css_get_scmi_info(idx); |
| 371 | scmi_channels[idx].lock = ARM_SCMI_LOCK_GET_INSTANCE; |
| 372 | scmi_handles[idx] = scmi_init(&scmi_channels[idx]); |
| 373 | |
| 374 | if (scmi_handles[idx] == NULL) { |
| 375 | ERROR("SCMI Initialization failed on channel %d\n", idx); |
| 376 | panic(); |
| 377 | } |
| 378 | |
| 379 | if (scmi_ap_core_init(&scmi_channels[idx]) < 0) { |
| 380 | ERROR("SCMI AP core protocol initialization failed\n"); |
| 381 | panic(); |
| 382 | } |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 383 | } |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 384 | |
| 385 | composite_id = plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()]; |
| 386 | default_scmi_channel_id = GET_SCMI_CHANNEL_ID(composite_id); |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 387 | } |
| 388 | |
| 389 | /****************************************************************************** |
| 390 | * This function overrides the default definition for ARM platforms. Initialize |
| 391 | * the SCMI driver, query capability via SCMI and modify the PSCI capability |
| 392 | * based on that. |
| 393 | *****************************************************************************/ |
Chandni Cherukuri | e4bf6a0 | 2018-11-14 13:43:59 +0530 | [diff] [blame] | 394 | const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops) |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 395 | { |
| 396 | uint32_t msg_attr; |
| 397 | int ret; |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 398 | void *scmi_handle = scmi_handles[default_scmi_channel_id]; |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 399 | |
| 400 | assert(scmi_handle); |
| 401 | |
| 402 | /* Check that power domain POWER_STATE_SET message is supported */ |
| 403 | ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, |
| 404 | SCMI_PWR_STATE_SET_MSG, &msg_attr); |
| 405 | if (ret != SCMI_E_SUCCESS) { |
| 406 | ERROR("Set power state command is not supported by SCMI\n"); |
| 407 | panic(); |
| 408 | } |
| 409 | |
| 410 | /* |
| 411 | * Don't support PSCI NODE_HW_STATE call if SCMI doesn't support |
| 412 | * POWER_STATE_GET message. |
| 413 | */ |
| 414 | ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, |
| 415 | SCMI_PWR_STATE_GET_MSG, &msg_attr); |
| 416 | if (ret != SCMI_E_SUCCESS) |
| 417 | ops->get_node_hw_state = NULL; |
| 418 | |
| 419 | /* Check if the SCMI SYSTEM_POWER_STATE_SET message is supported */ |
| 420 | ret = scmi_proto_msg_attr(scmi_handle, SCMI_SYS_PWR_PROTO_ID, |
| 421 | SCMI_SYS_PWR_STATE_SET_MSG, &msg_attr); |
| 422 | if (ret != SCMI_E_SUCCESS) { |
| 423 | /* System power management operations are not supported */ |
| 424 | ops->system_off = NULL; |
| 425 | ops->system_reset = NULL; |
| 426 | ops->get_sys_suspend_power_state = NULL; |
Roberto Vargas | 3caafd7 | 2017-08-16 08:57:45 +0100 | [diff] [blame] | 427 | } else { |
| 428 | if (!(msg_attr & SCMI_SYS_PWR_SUSPEND_SUPPORTED)) { |
| 429 | /* |
| 430 | * System power management protocol is available, but |
| 431 | * it does not support SYSTEM SUSPEND. |
| 432 | */ |
| 433 | ops->get_sys_suspend_power_state = NULL; |
| 434 | } |
| 435 | if (!(msg_attr & SCMI_SYS_PWR_WARM_RESET_SUPPORTED)) { |
| 436 | /* |
| 437 | * WARM reset is not available. |
| 438 | */ |
| 439 | ops->system_reset2 = NULL; |
| 440 | } |
Soby Mathew | ea26bad | 2016-11-14 12:25:45 +0000 | [diff] [blame] | 441 | } |
| 442 | |
| 443 | return ops; |
| 444 | } |
Roberto Vargas | 3caafd7 | 2017-08-16 08:57:45 +0100 | [diff] [blame] | 445 | |
| 446 | int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie) |
| 447 | { |
| 448 | if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET)) |
| 449 | return PSCI_E_INVALID_PARAMS; |
| 450 | |
| 451 | css_scp_system_off(SCMI_SYS_PWR_WARM_RESET); |
| 452 | /* |
| 453 | * css_scp_system_off cannot return (it is a __dead function), |
| 454 | * but css_system_reset2 has to return some value, even in |
| 455 | * this case. |
| 456 | */ |
| 457 | return 0; |
| 458 | } |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 459 | |
| 460 | #if PROGRAMMABLE_RESET_ADDRESS |
| 461 | void plat_arm_program_trusted_mailbox(uintptr_t address) |
| 462 | { |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 463 | int ret, i; |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 464 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 465 | for (i = 0; i < PLAT_ARM_SCMI_CHANNEL_COUNT; i++) { |
| 466 | assert(scmi_handles[i]); |
| 467 | |
| 468 | ret = scmi_ap_core_set_reset_addr(scmi_handles[i], address, |
| 469 | SCMI_AP_CORE_LOCK_ATTR); |
| 470 | if (ret != SCMI_E_SUCCESS) { |
| 471 | ERROR("CSS: Failed to program reset address: %d\n", ret); |
| 472 | panic(); |
| 473 | } |
Dimitris Papastamos | d7a3651 | 2018-06-18 13:01:06 +0100 | [diff] [blame] | 474 | } |
| 475 | } |
| 476 | #endif |