| Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | |
| 8 | #ifndef BOOT_INIT_DRAM_REGDEF_E3_H_ |
| 9 | #define BOOT_INIT_DRAM_REGDEF_E3_H_ |
| 10 | |
| 11 | #ifdef __cplusplus |
| 12 | extern "C" { |
| 13 | #endif /* __cplusplus */ |
| 14 | |
| 15 | #define BIT0 0x00000001U |
| 16 | #define BIT11 0x00000800U |
| 17 | #define BIT30 0x40000000U |
| 18 | |
| 19 | /* DBSC registers */ |
| 20 | |
| 21 | #define DBSC_E3_DBSYSCONF1 0xE6790004U |
| 22 | #define DBSC_E3_DBPHYCONF0 0xE6790010U |
| 23 | #define DBSC_E3_DBKIND 0xE6790020U |
| 24 | #define DBSC_E3_DBMEMCONF00 0xE6790030U |
| 25 | #define DBSC_E3_DBSYSCNT0 0xE6790100U |
| 26 | #define DBSC_E3_DBACEN 0xE6790200U |
| 27 | #define DBSC_E3_DBRFEN 0xE6790204U |
| 28 | #define DBSC_E3_DBCMD 0xE6790208U |
| 29 | #define DBSC_E3_DBWAIT 0xE6790210U |
| 30 | #define DBSC_E3_DBTR0 0xE6790300U |
| 31 | #define DBSC_E3_DBTR1 0xE6790304U |
| 32 | #define DBSC_E3_DBTR2 0xE6790308U |
| 33 | #define DBSC_E3_DBTR3 0xE679030CU |
| 34 | #define DBSC_E3_DBTR4 0xE6790310U |
| 35 | #define DBSC_E3_DBTR5 0xE6790314U |
| 36 | #define DBSC_E3_DBTR6 0xE6790318U |
| 37 | #define DBSC_E3_DBTR7 0xE679031CU |
| 38 | #define DBSC_E3_DBTR8 0xE6790320U |
| 39 | #define DBSC_E3_DBTR9 0xE6790324U |
| 40 | #define DBSC_E3_DBTR10 0xE6790328U |
| 41 | #define DBSC_E3_DBTR11 0xE679032CU |
| 42 | #define DBSC_E3_DBTR12 0xE6790330U |
| 43 | #define DBSC_E3_DBTR13 0xE6790334U |
| 44 | #define DBSC_E3_DBTR14 0xE6790338U |
| 45 | #define DBSC_E3_DBTR15 0xE679033CU |
| 46 | #define DBSC_E3_DBTR16 0xE6790340U |
| 47 | #define DBSC_E3_DBTR17 0xE6790344U |
| 48 | #define DBSC_E3_DBTR18 0xE6790348U |
| 49 | #define DBSC_E3_DBTR19 0xE679034CU |
| 50 | #define DBSC_E3_DBTR20 0xE6790350U |
| 51 | #define DBSC_E3_DBTR21 0xE6790354U |
| 52 | #define DBSC_E3_DBBL 0xE6790400U |
| 53 | #define DBSC_E3_DBRFCNF1 0xE6790414U |
| 54 | #define DBSC_E3_DBRFCNF2 0xE6790418U |
| 55 | #define DBSC_E3_DBCALCNF 0xE6790424U |
| 56 | #define DBSC_E3_DBODT0 0xE6790460U |
| 57 | #define DBSC_E3_DBADJ0 0xE6790500U |
| 58 | #define DBSC_E3_DBDFICUPDCNF 0xE679052CU |
| 59 | #define DBSC_E3_DBDFICNT0 0xE6790604U |
| 60 | #define DBSC_E3_DBPDLK0 0xE6790620U |
| 61 | #define DBSC_E3_DBPDRGA0 0xE6790624U |
| 62 | #define DBSC_E3_DBPDRGD0 0xE6790628U |
| 63 | #define DBSC_E3_DBBUS0CNF1 0xE6790804U |
| 64 | #define DBSC_E3_DBCAM0CNF1 0xE6790904U |
| 65 | #define DBSC_E3_DBCAM0CNF2 0xE6790908U |
| 66 | #define DBSC_E3_DBCAM0STAT0 0xE6790980U |
| 67 | #define DBSC_E3_DBBCAMDIS 0xE67909FCU |
| 68 | #define DBSC_E3_DBSCHCNT0 0xE6791000U |
| 69 | #define DBSC_E3_DBSCHSZ0 0xE6791010U |
| 70 | #define DBSC_E3_DBSCHRW0 0xE6791020U |
| 71 | #define DBSC_E3_DBSCHRW1 0xE6791024U |
| 72 | #define DBSC_E3_DBSCHQOS00 0xE6791030U |
| 73 | #define DBSC_E3_DBSCHQOS01 0xE6791034U |
| 74 | #define DBSC_E3_DBSCHQOS02 0xE6791038U |
| 75 | #define DBSC_E3_DBSCHQOS03 0xE679103CU |
| 76 | #define DBSC_E3_DBSCHQOS40 0xE6791070U |
| 77 | #define DBSC_E3_DBSCHQOS41 0xE6791074U |
| 78 | #define DBSC_E3_DBSCHQOS42 0xE6791078U |
| 79 | #define DBSC_E3_DBSCHQOS43 0xE679107CU |
| 80 | #define DBSC_E3_DBSCHQOS90 0xE67910C0U |
| 81 | #define DBSC_E3_DBSCHQOS91 0xE67910C4U |
| 82 | #define DBSC_E3_DBSCHQOS92 0xE67910C8U |
| 83 | #define DBSC_E3_DBSCHQOS93 0xE67910CCU |
| 84 | #define DBSC_E3_DBSCHQOS130 0xE6791100U |
| 85 | #define DBSC_E3_DBSCHQOS131 0xE6791104U |
| 86 | #define DBSC_E3_DBSCHQOS132 0xE6791108U |
| 87 | #define DBSC_E3_DBSCHQOS133 0xE679110CU |
| 88 | #define DBSC_E3_DBSCHQOS140 0xE6791110U |
| 89 | #define DBSC_E3_DBSCHQOS141 0xE6791114U |
| 90 | #define DBSC_E3_DBSCHQOS142 0xE6791118U |
| 91 | #define DBSC_E3_DBSCHQOS143 0xE679111CU |
| 92 | #define DBSC_E3_DBSCHQOS150 0xE6791120U |
| 93 | #define DBSC_E3_DBSCHQOS151 0xE6791124U |
| 94 | #define DBSC_E3_DBSCHQOS152 0xE6791128U |
| 95 | #define DBSC_E3_DBSCHQOS153 0xE679112CU |
| 96 | #define DBSC_E3_SCFCTST0 0xE6791700U |
| 97 | #define DBSC_E3_SCFCTST1 0xE6791708U |
| 98 | #define DBSC_E3_SCFCTST2 0xE679170CU |
| 99 | |
| 100 | /* CPG registers */ |
| 101 | |
| 102 | #define CPG_SRCR4 0xE61500BCU |
| 103 | #define CPG_PLLECR 0xE61500D0U |
| 104 | #define CPG_CPGWPR 0xE6150900U |
| 105 | #define CPG_CPGWPCR 0xE6150904U |
| 106 | #define CPG_SRSTCLR4 0xE6150950U |
| 107 | |
| 108 | /* MODE Monitor registers */ |
| 109 | |
| 110 | #define RST_MODEMR 0xE6160060U |
| 111 | |
| 112 | #ifdef __cplusplus |
| 113 | } |
| 114 | #endif /* __cplusplus */ |
| 115 | #endif /* BOOT_INIT_DRAM_REGDEF_E3_H_ */ |