Sandrine Bailleux | 27866d8 | 2013-10-25 15:33:39 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 27866d8 | 2013-10-25 15:33:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __GIC_V2_H__ |
| 32 | #define __GIC_V2_H__ |
| 33 | |
Dan Handley | 930ee2e | 2014-04-17 17:48:52 +0100 | [diff] [blame] | 34 | |
| 35 | #define GIC400_NUM_SPIS 480 |
| 36 | #define MAX_PPIS 14 |
| 37 | #define MAX_SGIS 16 |
| 38 | |
| 39 | #define GRP0 0 |
| 40 | #define GRP1 1 |
| 41 | #define GIC_PRI_MASK 0xff |
| 42 | #define GIC_HIGHEST_SEC_PRIORITY 0 |
| 43 | #define GIC_LOWEST_SEC_PRIORITY 127 |
| 44 | #define GIC_HIGHEST_NS_PRIORITY 128 |
| 45 | #define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ |
| 46 | |
| 47 | #define ENABLE_GRP0 (1 << 0) |
| 48 | #define ENABLE_GRP1 (1 << 1) |
| 49 | |
| 50 | /* Distributor interface definitions */ |
| 51 | #define GICD_CTLR 0x0 |
| 52 | #define GICD_TYPER 0x4 |
| 53 | #define GICD_IGROUPR 0x80 |
| 54 | #define GICD_ISENABLER 0x100 |
| 55 | #define GICD_ICENABLER 0x180 |
| 56 | #define GICD_ISPENDR 0x200 |
| 57 | #define GICD_ICPENDR 0x280 |
| 58 | #define GICD_ISACTIVER 0x300 |
| 59 | #define GICD_ICACTIVER 0x380 |
| 60 | #define GICD_IPRIORITYR 0x400 |
| 61 | #define GICD_ITARGETSR 0x800 |
| 62 | #define GICD_ICFGR 0xC00 |
| 63 | #define GICD_SGIR 0xF00 |
| 64 | #define GICD_CPENDSGIR 0xF10 |
| 65 | #define GICD_SPENDSGIR 0xF20 |
| 66 | |
| 67 | #define IGROUPR_SHIFT 5 |
| 68 | #define ISENABLER_SHIFT 5 |
| 69 | #define ICENABLER_SHIFT ISENABLER_SHIFT |
| 70 | #define ISPENDR_SHIFT 5 |
| 71 | #define ICPENDR_SHIFT ISPENDR_SHIFT |
| 72 | #define ISACTIVER_SHIFT 5 |
| 73 | #define ICACTIVER_SHIFT ISACTIVER_SHIFT |
| 74 | #define IPRIORITYR_SHIFT 2 |
| 75 | #define ITARGETSR_SHIFT 2 |
| 76 | #define ICFGR_SHIFT 4 |
| 77 | #define CPENDSGIR_SHIFT 2 |
| 78 | #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT |
| 79 | |
| 80 | /* GICD_TYPER bit definitions */ |
| 81 | #define IT_LINES_NO_MASK 0x1f |
| 82 | |
| 83 | /* Physical CPU Interface registers */ |
| 84 | #define GICC_CTLR 0x0 |
| 85 | #define GICC_PMR 0x4 |
| 86 | #define GICC_BPR 0x8 |
| 87 | #define GICC_IAR 0xC |
| 88 | #define GICC_EOIR 0x10 |
| 89 | #define GICC_RPR 0x14 |
| 90 | #define GICC_HPPIR 0x18 |
| 91 | #define GICC_IIDR 0xFC |
| 92 | #define GICC_DIR 0x1000 |
| 93 | #define GICC_PRIODROP GICC_EOIR |
| 94 | |
| 95 | /* GICC_CTLR bit definitions */ |
| 96 | #define EOI_MODE_NS (1 << 10) |
| 97 | #define EOI_MODE_S (1 << 9) |
| 98 | #define IRQ_BYP_DIS_GRP1 (1 << 8) |
| 99 | #define FIQ_BYP_DIS_GRP1 (1 << 7) |
| 100 | #define IRQ_BYP_DIS_GRP0 (1 << 6) |
| 101 | #define FIQ_BYP_DIS_GRP0 (1 << 5) |
| 102 | #define CBPR (1 << 4) |
| 103 | #define FIQ_EN (1 << 3) |
| 104 | #define ACK_CTL (1 << 2) |
| 105 | |
| 106 | /* GICC_IIDR bit masks and shifts */ |
| 107 | #define GICC_IIDR_PID_SHIFT 20 |
| 108 | #define GICC_IIDR_ARCH_SHIFT 16 |
| 109 | #define GICC_IIDR_REV_SHIFT 12 |
| 110 | #define GICC_IIDR_IMP_SHIFT 0 |
| 111 | |
| 112 | #define GICC_IIDR_PID_MASK 0xfff |
| 113 | #define GICC_IIDR_ARCH_MASK 0xf |
| 114 | #define GICC_IIDR_REV_MASK 0xf |
| 115 | #define GICC_IIDR_IMP_MASK 0xfff |
| 116 | |
| 117 | /* HYP view virtual CPU Interface registers */ |
| 118 | #define GICH_CTL 0x0 |
| 119 | #define GICH_VTR 0x4 |
| 120 | #define GICH_ELRSR0 0x30 |
| 121 | #define GICH_ELRSR1 0x34 |
| 122 | #define GICH_APR0 0xF0 |
| 123 | #define GICH_LR_BASE 0x100 |
| 124 | |
| 125 | /* Virtual CPU Interface registers */ |
| 126 | #define GICV_CTL 0x0 |
| 127 | #define GICV_PRIMASK 0x4 |
| 128 | #define GICV_BP 0x8 |
| 129 | #define GICV_INTACK 0xC |
| 130 | #define GICV_EOI 0x10 |
| 131 | #define GICV_RUNNINGPRI 0x14 |
| 132 | #define GICV_HIGHESTPEND 0x18 |
| 133 | #define GICV_DEACTIVATE 0x1000 |
| 134 | |
| 135 | #ifndef __ASSEMBLY__ |
| 136 | |
Sandrine Bailleux | 27866d8 | 2013-10-25 15:33:39 +0100 | [diff] [blame] | 137 | #include <mmio.h> |
| 138 | |
Dan Handley | 930ee2e | 2014-04-17 17:48:52 +0100 | [diff] [blame] | 139 | |
| 140 | /******************************************************************************* |
| 141 | * GIC Distributor function prototypes |
| 142 | ******************************************************************************/ |
| 143 | |
| 144 | extern unsigned int gicd_read_igroupr(unsigned int, unsigned int); |
| 145 | extern unsigned int gicd_read_isenabler(unsigned int, unsigned int); |
| 146 | extern unsigned int gicd_read_icenabler(unsigned int, unsigned int); |
| 147 | extern unsigned int gicd_read_ispendr(unsigned int, unsigned int); |
| 148 | extern unsigned int gicd_read_icpendr(unsigned int, unsigned int); |
| 149 | extern unsigned int gicd_read_isactiver(unsigned int, unsigned int); |
| 150 | extern unsigned int gicd_read_icactiver(unsigned int, unsigned int); |
| 151 | extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); |
| 152 | extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int); |
| 153 | extern unsigned int gicd_read_icfgr(unsigned int, unsigned int); |
| 154 | extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); |
| 155 | extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int); |
| 156 | extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); |
| 157 | extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); |
| 158 | extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); |
| 159 | extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); |
| 160 | extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); |
| 161 | extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); |
| 162 | extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); |
| 163 | extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); |
| 164 | extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); |
| 165 | extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); |
| 166 | extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); |
| 167 | extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); |
| 168 | extern unsigned int gicd_get_igroupr(unsigned int, unsigned int); |
| 169 | extern void gicd_set_igroupr(unsigned int, unsigned int); |
| 170 | extern void gicd_clr_igroupr(unsigned int, unsigned int); |
| 171 | extern void gicd_set_isenabler(unsigned int, unsigned int); |
| 172 | extern void gicd_set_icenabler(unsigned int, unsigned int); |
| 173 | extern void gicd_set_ispendr(unsigned int, unsigned int); |
| 174 | extern void gicd_set_icpendr(unsigned int, unsigned int); |
| 175 | extern void gicd_set_isactiver(unsigned int, unsigned int); |
| 176 | extern void gicd_set_icactiver(unsigned int, unsigned int); |
| 177 | extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); |
| 178 | extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); |
| 179 | |
| 180 | |
Sandrine Bailleux | 27866d8 | 2013-10-25 15:33:39 +0100 | [diff] [blame] | 181 | /******************************************************************************* |
| 182 | * GIC Distributor interface accessors for reading entire registers |
| 183 | ******************************************************************************/ |
| 184 | |
| 185 | static inline unsigned int gicd_read_ctlr(unsigned int base) |
| 186 | { |
| 187 | return mmio_read_32(base + GICD_CTLR); |
| 188 | } |
| 189 | |
| 190 | static inline unsigned int gicd_read_typer(unsigned int base) |
| 191 | { |
| 192 | return mmio_read_32(base + GICD_TYPER); |
| 193 | } |
| 194 | |
| 195 | static inline unsigned int gicd_read_sgir(unsigned int base) |
| 196 | { |
| 197 | return mmio_read_32(base + GICD_SGIR); |
| 198 | } |
| 199 | |
| 200 | |
| 201 | /******************************************************************************* |
| 202 | * GIC Distributor interface accessors for writing entire registers |
| 203 | ******************************************************************************/ |
| 204 | |
| 205 | static inline void gicd_write_ctlr(unsigned int base, unsigned int val) |
| 206 | { |
| 207 | mmio_write_32(base + GICD_CTLR, val); |
| 208 | } |
| 209 | |
| 210 | static inline void gicd_write_sgir(unsigned int base, unsigned int val) |
| 211 | { |
| 212 | mmio_write_32(base + GICD_SGIR, val); |
| 213 | } |
| 214 | |
| 215 | |
| 216 | /******************************************************************************* |
| 217 | * GIC CPU interface accessors for reading entire registers |
| 218 | ******************************************************************************/ |
| 219 | |
| 220 | static inline unsigned int gicc_read_ctlr(unsigned int base) |
| 221 | { |
| 222 | return mmio_read_32(base + GICC_CTLR); |
| 223 | } |
| 224 | |
| 225 | static inline unsigned int gicc_read_pmr(unsigned int base) |
| 226 | { |
| 227 | return mmio_read_32(base + GICC_PMR); |
| 228 | } |
| 229 | |
| 230 | static inline unsigned int gicc_read_BPR(unsigned int base) |
| 231 | { |
| 232 | return mmio_read_32(base + GICC_BPR); |
| 233 | } |
| 234 | |
| 235 | static inline unsigned int gicc_read_IAR(unsigned int base) |
| 236 | { |
| 237 | return mmio_read_32(base + GICC_IAR); |
| 238 | } |
| 239 | |
| 240 | static inline unsigned int gicc_read_EOIR(unsigned int base) |
| 241 | { |
| 242 | return mmio_read_32(base + GICC_EOIR); |
| 243 | } |
| 244 | |
| 245 | static inline unsigned int gicc_read_hppir(unsigned int base) |
| 246 | { |
| 247 | return mmio_read_32(base + GICC_HPPIR); |
| 248 | } |
| 249 | |
| 250 | static inline unsigned int gicc_read_dir(unsigned int base) |
| 251 | { |
| 252 | return mmio_read_32(base + GICC_DIR); |
| 253 | } |
| 254 | |
| 255 | static inline unsigned int gicc_read_iidr(unsigned int base) |
| 256 | { |
| 257 | return mmio_read_32(base + GICC_IIDR); |
| 258 | } |
| 259 | |
| 260 | |
| 261 | /******************************************************************************* |
| 262 | * GIC CPU interface accessors for writing entire registers |
| 263 | ******************************************************************************/ |
| 264 | |
| 265 | static inline void gicc_write_ctlr(unsigned int base, unsigned int val) |
| 266 | { |
| 267 | mmio_write_32(base + GICC_CTLR, val); |
| 268 | } |
| 269 | |
| 270 | static inline void gicc_write_pmr(unsigned int base, unsigned int val) |
| 271 | { |
| 272 | mmio_write_32(base + GICC_PMR, val); |
| 273 | } |
| 274 | |
| 275 | static inline void gicc_write_BPR(unsigned int base, unsigned int val) |
| 276 | { |
| 277 | mmio_write_32(base + GICC_BPR, val); |
| 278 | } |
| 279 | |
| 280 | |
| 281 | static inline void gicc_write_IAR(unsigned int base, unsigned int val) |
| 282 | { |
| 283 | mmio_write_32(base + GICC_IAR, val); |
| 284 | } |
| 285 | |
| 286 | static inline void gicc_write_EOIR(unsigned int base, unsigned int val) |
| 287 | { |
| 288 | mmio_write_32(base + GICC_EOIR, val); |
| 289 | } |
| 290 | |
| 291 | static inline void gicc_write_hppir(unsigned int base, unsigned int val) |
| 292 | { |
| 293 | mmio_write_32(base + GICC_HPPIR, val); |
| 294 | } |
| 295 | |
| 296 | static inline void gicc_write_dir(unsigned int base, unsigned int val) |
| 297 | { |
| 298 | mmio_write_32(base + GICC_DIR, val); |
| 299 | } |
| 300 | |
Dan Handley | 930ee2e | 2014-04-17 17:48:52 +0100 | [diff] [blame] | 301 | #endif /*__ASSEMBLY__*/ |
| 302 | |
Sandrine Bailleux | 27866d8 | 2013-10-25 15:33:39 +0100 | [diff] [blame] | 303 | #endif /* __GIC_V2_H__ */ |